Get Ready For DVCon Europe

By Martin Barnasconi
DVCon Europe, a new conference and exhibition around design and verification, will be held Oct. 14-15 in Munich, Germany. Call for abstracts for DVCon Europe is open through April 8.

The obvious question is why DVCon Europe. DVCon and its predecessor conferences have been held successfully in the Silicon Valley for more than 20 years. The conference is extremely successful, with record numbers in attendance, exhibitors and papers this year. The primary reason for this success is that DVCon is a very technical and user-centric conference where experts in the field of design and verification come together to share their experiences on the application of EDA and IP standards, languages and methodologies.

DVCon Europe is a natural extension of this success, and it’s a much-needed conference in Europe. Complex system-level design, mixed-signal verification, design integration and automation are some of the challenges that chip designers are facing today. DVCon Europe will focus on user case studies and experiences on how to efficiently apply design and verification methods and tools in real life.

DVCon Europe is driven by European user companies because these companies see the value of having a user-centric technical conference in Europe. As such, DVCon Europe will be an industry-focused event with a clear technical focus on standards for system and IC design and verification. This means attendees of DVCon Europe will learn practical things that they can immediately apply in their own projects.

Conference Format
DVCon Europe will contain the same successful ingredients as DVCon Silicon Valley. This means we will keep the conference informal, where technical experts can network, interact easily with EDA and IP vendors and service providers, and focus on learning and sharing practical experiences in design and verification. There will be a small exhibition, which will facilitate technical discussions with these EDA and IP vendors and service providers. For a preview of what will happen at DVCon Europe, have a look at this video we made recently at DVCon Silicon Valley.

From a program point of view, we will select papers and posters using a highly industry-centric technical review committee. In terms of technical content, we will target the same areas as DVCon Silicon Valley, addressing system-level design, verification & validation, IP reuse and design automation as well as mixed-signal and low-power design and verification. We expect many papers and posters on SystemC, SystemVerilog, the Universal Verification Methodology (UVM), IP-XACT and much more. Knowing the user base in Europe, we foresee a strong interest in Electronic System Level (ESL) and mixed-signal design and verification. Interestingly enough, verification methodologies such as UVM are not yet widespread in Europe, so we expect a tutorial session on UVM would be well attended.

Accellera’s Role
Accellera Systems Initiative is the conference sponsor of DVCon Europe. In Europe, the Open SystemC Initiative (OSCI) standardization organization was well known, primarily due to the use and promotion of SystemC. After the OSCI merger with Accellera, language EDA and IP standards development has become less visible in Europe, despite the fact that the entire industry fully relies on the system, IP and hardware description languages and methodologies developed within Accellera. As Accellera’s mission is to provide design and verification standards to further enhance the front-end design automation process, our ambition is to further strengthen the collaboration with the European user companies and organizations. For example, we’ve seen analog/mixed-signal extensions developed for SystemC and IP-XACT, and these have been primarily driven by user companies in Europe. In addition, the Electronic Chips & Systems design Initiative (ECSI) is helping to organize DVCon Europe and is organizing the Forum on specification & Design Languages (FDL) as a co-located event at DVCon Europe.

The objectives of DVCon Europe are to bring people active in Accellera standardization and end users closer together, where not only the participants will learn a lot, but they will also start to exchange ideas and discuss developments on the next version — or even the next generation— of EDA and IP languages in design and verification.

Therefore, I invite our system and IC design and verification community to submit abstracts to DVCon Europe! Please visit www.dvcon-europe.org for more details on the submission process. The call for abstracts is open through April 8, 2014. I am looking forward to meeting you all at DVCon Europe!

Martin Barnasconi is general chair of DVCon Europe and member of the Board of Directors of Accellera Systems Initiative.