Getting Ready For The IoT

Preparing for the next seismic shift in the semiconductor industry.


A major change is underway in the semiconductor industry, and it is being driven by the Internet of Things. Gartner defines the IoT as a “network of dedicated physical objects (things) that contain embedded technology to sense or interact with their internal state or external environment. The IoT comprises an ecosystem that includes things, communication, applications and data analysis.”

The market research firm “forecasts that 4.9 billion connected things will be in use in 2015, up 30% from 2014, and will reach 25 billion by 2020.” The IoT is a powerful force for business transformation, and its disruptive impact will be felt across all industries and all areas of society.

In the past, the major driver of the industry was the PC, then the mobile phone and its associated devices. These product categories demanded a certain type of CPU architecture. The PC was driven by CPUs with ever-increasing MIPS. The mobile phone demanded MIPS surrounded by coprocessors to handle specialized functions—video, audio, position location, camera, low-energy Bluetooth links to a wide variety of external devices. With the advent of IoT, the CPU is now in intelligent sensing devices demanding MIPS but with extreme battery life. For the PC, power was less a concern than for the mobile phone, which could rely on regular intervals of battery recharge. Both, however, demanded increased security. For the IoT device, power is the ultimate concern, followed by performance and security.

The CPU architectures that serve the PC and mobile phone were created with their unique operating requirements in mind. With the advent of IoT, both architectures have attempted to accommodate the extreme power requirements of IoT devices: years of battery life, 32-bit CPU performance, and unique security demanded by unattended operation. Andes determined that IoT applications require a CPU architecture designed with these unique capabilities built in, not retrofitted on top of an architecture designed for mobile phones and PCs. Furthermore, the years of legacy software constrains older architectures from major alterations to deliver the demands of IoT applications.

Having the advantage of not needing to support a huge legacy installed base is a benefit when it comes to IoT devices, which need to have years of battery life. Architectures require enormous power savings while providing high performance, and hacker-resistant security includes such features as frequency throttling, patented memory architecture, and custom instructions.

One technique is to balance a low-cost (few gates) way of achieving CPU frequency scaling without changing the PLL clock. This is especially important for intelligent sensors, which spend large amounts of time waiting for an input, brief periods of complex computation, short periods of compressing data and communicating it to an external device.

The major performance and power bottleneck in an IoT device is the flash memory containing its program. A good approach to breaking this bottleneck is to use a small amount of cache—tiny cache—and a pre-fetch SRAM buffer. Running the Coremark and DMIPS benchmarks using this technique can boost those scores from 30% to 80%. That approach also allows the designer to achieve the same DMIPS performance with a lower clock or maintain the clock and boost the DMIPS performance.

Adding custom instructions to accelerate compute-intensive tasks is another valuable technique. For example, a custom instruction to accelerate a FIR filter can boost performance and reduce power consumption by as much as an order of magnitude. While custom instructions are not new to embedded processors, they now can be incorporated it into the existing software development tools with quick turnaround time.

Just as architectural elements are added for power, so too for security against hacking. These elements include physical security such as secure interrupt with hardware memory stacking, data and address scrambling, and differential power analysis protection. The first of these three protects the CPU states (including register file and program stack) of secure software (such as a crypto function) from the potential attack via a malicious ISR (interrupt service routine) without compromising the real-time response of harmless cooperative ISR’s. Scrambling defends against attacks that target the interface between CPU and memory. Power analysis protection guards against hacking the program by observing the power use signature of the CPU. This is achieved by scrambling the power profile of the CPU to make it unintelligible to an attacker.

Another security vulnerability is the debug port found on most chips for software upgrade and maintenance during design and for bug fixes in the field. To eliminate the vulnerability, many SoC designs remove the debug port before final silicon. The best solution is to use a secure embedded debug module that allows designers to fix software in the field while guarding against physical hacking attacks.

Today’s Internet-of-Things device needs embedded processing capability that can deliver low cost, low power consumption and high security. Older 8-bit CPUs currently used in many IoT devices lack the processing power and architectural features to efficiently deliver these three critical IoT functions. Furthermore, many of the 32-bit embedded cores designed for server and smart phone applications are lacking the architectural features to deliver low cost, hardware security, and ultra low power savings. The AndesCore series of high performance 32-bit CPU cores, designed in the past decade, have all these IoT demanded elements included.

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