Harness System-Level Data To Optimize Many-Core AI And ML Chips

Issues and solutions for SoC validation and optimization.


The novel multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications are expected to deliver huge improvements in power efficiency. However, chip development teams and the customers for their devices face the growing complexity of hardware-software co-optimization, validation, and debug. In short, these SoCs are increasingly difficult to validate and optimize.

SoC development and software teams must be able to monitor the behavior and performance of applications in both the pre- and post-deployment phases. An embedded functional analytics architecture establishes the chip visibility needed to capture accurate data about on-chip behavior in real-time. This paper describes the Tessent Embedded Analytics platform of silicon IP, software tools, and libraries that provide system-level data visibility and functional analysis. Tessent Embedded Analytics works across the wide range of many-core and heterogeneous architectures that are employed to meet the demands of today’s processing workloads. and enables development teams to harness functional data for system-level optimization.

The impact of many-core architectures on functional analysis
AI-driven SoC architectures introduce new levels of complexity in system and software design. Failure to meet the needs of both chip and software development teams to validate and optimize their designs, applications, drivers, and libraries can take a massive toll on productivity, delay product launch, and reduce customer adoption. A piecemeal solution based on processor-centric debug and software instrumentation will likely make root-cause analysis difficult or impossible. Equally, an insufficiently granular network of interconnect monitors may lead to performance being left on the table. It may prove impossible to tune distributed software to take full advantage of the SoC’s parallelism because developers cannot gain sufficient visibility on interactions between threads and how they use shared memory.

By designing in a functional analytics architecture that recognizes those needs early in the project, you can optimize the on-chip analytics infrastructure for data visibility and silicon cost. With the right level of visibility, validation can proceed quickly even in the simulation and emulation environments used for pre-silicon design. That, in turn, helps identify bugs and inefficiencies in the hardware design that would otherwise hinder market adoption. As the embedded system moves into the phase of HW-SW co-optimization, a highly configurable, system-level data platform enables rapid cycles of testing and learning, leading to higher quality, more performant systems.

Understanding the issues involved in implementing an effective system validation and optimization environment is key to the successful delivery of many-core SoCs and is a key reason why working with a supplier with deep expertise in this area is essential. The Tessent Embedded Analytics team is here to work with many-core SoC architects and software teams to provide the system-level data visibility they need for the AI-driven systems they are building.

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