High Performance, Low Power, And Test: DFT’s Impact On System PPA And Safety

Back in the day, test was an afterthought in system design and implementation. It was a separate task that could be added to the end of a project schedule—essentially, a checkbox before sending a design for manufacture or during product qualification. Nowadays, test is no longer an afterthought, and we’ll see it continue to grow in importance.

Safety-critical semiconductor applications have driven test squarely into the functional specification and system architecture stages of design. Without the proper consideration of test, high levels of coverage in short test times is impractical. Safety cannot be an afterthought. A poorly integrated test strategy results in negative impacts to system performance, power consumption, and in obtaining safety certification for the final product.

To achieve the high levels of diagnostic coverage in a short time interval for in-system test, built-in self-test (BIST) is often used. However, this cannot be applied carelessly to the system without incurring a massive power, performance, and area (PPA) penalty, facing a serious risk of failure to meet the in-system fault tolerant time interval (FTTI). Designers must have an understanding of test requirements while architecting the system. A partitioned approach will use BIST only on the most safety-critical sub-circuits for in-system test with short FTTI and test a larger portion of the design with BIST at power-on when the FTTI is much more relaxed.

Designers also rely on memory BIST (MBIST). Poor partitioning of MBIST could result in high-power density during self-test. Understanding the physical arrangement of the logical memories and the BIST sequencing spreads the activity out and decreases the risk of a power integrity issue.

EDA has helped with this problem through two key developments: 1.) Using RTL-insertion for test circuitry, and 2.) Changing how test is integrated natively with the overall EDA tools, flows, and methodology.

The first development, RTL-insertion, for items like MBIST, is necessary to help the functional system verification. If the test circuitry is inserted only after the synthesis is complete, full system verification will be forced to run slow, expensive gate-level simulations. Adding in the critical test circuits in behavioral RTL allows higher-capacity simulation. This gives access to a broader set of tests earlier in the design lifecycle and helps increase confidence in the system architecture. The added benefit of RTL insertion is the use of RTL stimuli to help with system-level power and thermal analysis. Checking a larger set of system software early gives designers a better picture of potential reliability issues, and allows them to address power problems earlier in the design cycle.

The second development in the EDA flow itself integrates test into the entire process. Adding timing and power analysis to the implementation stage has allowed designers to produce a vastly improved performance with lower power. Similarly, sharing algorithms and data between synthesis and place-and-route provides more predictable paths to convergence. Physical synthesis is an example of this. Until recently, test has occurred outside of this loop. Native integration of test alongside RTL synthesis allows the PPA impacts of test to be visible when the EDA tools have the most flexibility to help solve those issues. Assigning scan chains and scan compression as native parts of the physical synthesis flow produces a drastic reduction in the routing resources and eases design convergence. Solely dealing with this in the RTL or as a post-synthesis ECO without consideration of the physical impact requires the designer to pay a very costly penalty in PPA, schedule, or both.

This trend of innovation and integration continues. Broadly adopting high-level synthesis in imaging and DSP systems requires a tight relationship with design-for-test (DFT). It’s an exciting time to be test in the EDA industry.