Hitting The Power Integrity Wall At 10nm

At 10nm and beyond, the breakdown of some historic trends tied to Moore’s Law is making it harder to fully harvest the benefits of scaling semiconductor technologies.

Underlying the power, performance and area benefits of scaling are technological challenges that must be solved in order to make the semiconductor products a profitable business. Power-related challenges are among the most pressing at 10nm:

• Increasing power density, the number of watts of power used in each square millimeter of the IC;
• Increasing sheet resistance, the ohmic resistance in the on-chip metal that distributes the power to the transistors, and
• Increasing power transients from faster transistor switching times.

This combination of trends worsens power integrity, in particular dynamic power integrity, which is embodied in the measure of dynamic voltage drop (DVD). Lower supply voltages put pressure on DVD margins. Tight timing and increasing timing variability put pressure on cycle-to-cycle DVD, which leads to clock jitter. Facing increasing power density, high metal sheet resistance and increasing power transients, the DVD margins become ever more difficult to achieve with existing tools.

The power integrity gap, as illustrated in Figure 1, is the gap between an IC’s inherent power integrity, as achieved using mainstream EDA tools and techniques, and the worst power integrity allowed for the IC to function properly, the power integrity wall.

The problems caused by diminishing power integrity are multifold. To achieve the tight DVD requirements, the power grid is taking increasing amounts of on-chip routing resources. This impacts routability.

Routability is a major concern at scaling process nodes, because transistors scale faster than wires, and leads to impairment in area utilization. Increasing IC area leads to higher cost, higher power consumption and lower performance. The only traditional way to solve this conundrum is to make the IC larger, which goes against the very idea — technologically and economically — of scaling altogether.

Another approach to achieve DVD requirements is to add on-chip decoupling capacitors (decaps). This is also costly in terms of area, and hence production cost. Decaps also pose a potential power grid stability issue. Resonance with inductive package leads can be a very serious challenge, especially at sub-clock frequencies, as the issue becomes program runtime dependent. In power-gated designs, using decaps pose another problem because it directly increases switch-on time. Decaps in the local power region must be charged slowly enough to avoid destabilizing the circuit. The more decaps, the slower switch-on time.

Figure 1: Trends of key parameters of integrated circuits with evolving technology nodes. (+) and (-) indicates whether the trend of a given parameter is a good or bad.

As such, power integrity challenges stand in the way of exploiting the technological and economic benefits of semiconductor scaling. A new paradigm of design optimization is needed, with power integrity as an integral and central parameter throughout the design implementation flow. The mainstream adaptation of power integrity sign-off was an important first step. However, the current power integrity-wise ‘black box’, which leaves the designer blind to power integrity issues until the detailed sign-off view at the very end of the flow, does not allow for optimal utilization of design resources – or even convergence.

A new breed of multi-parameter tools is needed to address this multifaceted challenge. Teklatech’s FloorDirector, already used in multiple 10nm production tapeouts and planned for use at 7nm, is one such tool. It alleviates the power integrity challenge by working holistically and intelligently to optimize designs. It identifies solutions in complex solution spaces with many interrelated cost dimensions, balancing a range of design parameters such as timing, power and placement, in its optimization efforts. This allows IC vendors to harvest more fully the economic benefits of semiconductor scaling.

Looking past finFETs, the IC design challenges increase further, as gate length scaling stalls and new device structures, such as vertical nanowire gate transistors and monolithic 3D structures, fuel the requirement of increasing compute performance at low power.