Achieving optimal PPA requires making some tradeoffs, and a better methodology for understanding those tradeoffs.
For complex, advanced-node designs, there’s a tug-of-war brewing between oft-conflicting goals around performance, power, and area (PPA) and turnaround time (TAT). Both are important for design success, yet it can be difficult to achieve optimal PPA with the highest productivity—without making any tradeoffs. At the root of this problem is that with traditional place-and-route tools, designers need to break the systems on chip (SoCs) into many small blocks. Breaking the SoCs into small blocks, in turn, makes it challenging to achieve optimal PPA and TAT. This paper discusses new digital implementation technology that equips you to handle larger size blocks and meet stringent PPA and TAT goals for SoCs at advanced 16/14/10nm FinFET as well as established process nodes.
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