Time To Rethink Memory Chip Design And Verification

It’s no secret to anyone that semiconductor development grows more challenging all the time. Each new process technology node packs more transistors into each die, creating more electrical issues and making heat dissipation harder. Floorplanning, logic synthesis, place and route, timing analysis, electrical analysis, and functional verification stretch electronic design automation (EDA) tools... » read more

Battling Fab Cycle Times

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Mask Maker Worries Grow

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

How To Achieve Optimal PPA And Up To 10X TAT Gain In Your Next Digital Design Implementation

For complex, advanced-node designs, there’s a tug-of-war brewing between oft-conflicting goals around performance, power, and area (PPA) and turnaround time (TAT). Both are important for design success, yet it can be difficult to achieve optimal PPA with the highest productivity—without making any tradeoffs. At the root of this problem is that with traditional place-and-route tools, designe... » read more