HW/SW Co-Verification For Hybrid Systems

Heterogeneous SoC architectures such as Zynq have become very popular recently due to the combination of programmable logic (FPGA) and processing system (ARM) integrated into a single chip. Developing a design using such hybrid systems causes complexity in design verification stages. To help address this complexity, Aldec introduced support for QEMU for co-verification in our HES.Proto-AXI host to FPGA bridge solution.

QEMU is an open-source machine emulator and virtualizer that emulates a wide range of CPU architectures. Together with a HW/SW co-simulation platform, it simplifies the verification process for challenging hybrid designs.

The question is how to comprehensively test such mixed technology devices. Hybrid devices require a hybrid verification environment, and there is more than one option available.

QEMU with Aldec tools
There are several places in the whole range of Aldec products and tools that QEMU fits perfectly. The most general breakdown can be made based on the project requirements:

• Verification of the well-known, available on the market SoC, such as Xilinx Zynq devices
• Verification of the custom designs, such as ASICs, where system architecture is project dependent. The verification environment is flexible and easy to apply to such systems.

Based on the above division, we offer two solutions: QEMU for Zynq/Zynq MPSoC and QEMU for HES emulation and prototyping.

QEMU co-simulation for Xilinx Zynq 7000/Zynq MPSoC devices
To co-simulate the designs that are based on Xilinx Zynq 7000 / MPSoC devices, Aldec has provided a HW/SW Co-Simulation solution using Riviera-Pro (Advance RTL simulator) and Xilinx QEMU. This solution is provided on the TySOM EDK package, which simplifies the hybrid verification for Xilinx Zynq devices. This integration makes an environment for engineers to verify the entire SoC (processing system and programmable logic) simultaneously. Separate tests for CPU and FPGA are no longer the only testing method. This solution utilizes Xilinx QEMU and connects it to Riviera-PRO, giving a comprehensive environment for testing Linux, drivers, or standalone processor applications with FPGA design in the simulator.

Figure 1: Xilinx Zynq/Zynq MPSoC QEMU and Riviera-PRO co-simulation

QEMU co-verification environment for emulation and prototyping
QEMU integration with Aldec emulation and prototyping products differs from the solution of Xilinx Zynq 7000/Zynq MPSoC. Years spent on the hardware-assisted verification market shown that one of the most important things is scalability to various verification modes. To achieve that we have adapted the official open-source QEMU to interact with:

• HES FPGA boards with Virtex-7, UltraScale and UltraScale+ devices in SCE-MI emulation flow
• HES FPGA boards with Virtex-7, UltraScale and UltraScale+ devices in HES.Proto-AXI prototyping solution flow
• Simulation of both, emulation and prototyping designs in Riviera-PRO

The architecture of the co-verification environment is shown in Figure 2.

Figure 2: Aldec QEMU emulation and prototyping co-verification environment

The environment consists of:

• QEMU – the official branch is used and integrated in order to achieve the CPU architecture flexibility. Currently (with the HES.Proto-AXI September release) the x86_64 and arm64 architectures are supported. What is worth emphasizing, when using x86_64 QEMU architecture on the same architecture of host PC it is possible to enable KVM virtualization. It results with the tremendous QEMU emulation speed, comparable to a host PC.
• PCI2AXI – a main device used in emulation and prototyping is AXI master connected to the QEMU emulated CPU as PCI device. For emulation, the debug device for Aldec debug tools controlling is available as well.
• HES board or Riviera-PRO simulator

Conclusion
The need for a comprehensive SoC verification is being noticed more and more due to the significant growth in demand for such devices. Having both HW/SW in an SoC design requires a hybrid environment to verify both and to make sure new changes don’t affect the entire design functionality. Aldec has paved this path by preparing a hybrid environment combining QEMU with Aldec verification, emulation and prototyping tools to solve the complexity of SoC verification process. This solution meets different verification requirements (Xilinx Zynq /Zynq MPSoC, ASIC emulation and prototyping) and offers various features. First of all, it corresponds to the architecture of SoC designs and gives an opportunity to test software and hardware live. It emulates different architecture CPUs, simplifies and accelerates cross-development between hardware and software/embedded engineering teams. Last but definitely not least – it’s integrated with Aldec SoC/ASIC/FPGA verification products such as HES high speed prototyping boards, HES-DVM, Riviera-PRO simulator and HES.Proto-AXI architecture.