Gaps In The AI Debug Process


When an AI algorithm is deployed in the field and gives an unexpected result, it's often not clear whether that result is correct. So what happened? Was it wrong? And if so, what caused the error? These are often not simple questions to answer. Moreover, as with all verification problems, the only way to get to the root cause is to break the problem down into manageable pieces. The semico... » read more

New Methodologies Create New Opportunities


Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardwa... » read more

HW/SW Co-Verification For Hybrid Systems


Heterogeneous SoC architectures such as Zynq have become very popular recently due to the combination of programmable logic (FPGA) and processing system (ARM) integrated into a single chip. Developing a design using such hybrid systems causes complexity in design verification stages. To help address this complexity, Aldec introduced support for QEMU for co-verification in our HES.Proto-AXI host... » read more

The Growing Impact Of Portable Stimulus


It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more