Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even when there are no obvious structural abnormalities in the underlying device. Leakage current has become a critically important component in DRAM device design.

Fig. 1 (a) DRAM Memory Cell, (b) GIDL in Cell Transistor, (c) Dielectric leakage between BLC and SNC, (d) Dielectric leakage at DRAM Capacitor

DRAM memory cells (Fig.1 (a)) must be constantly refreshed, since they lose stored data when power is turned off [1]. Retention time, or the amount of time that a cell can store data before data loss, is a critical characteristic of DRAM and can be limited by leakage current.

There are two important leakage components in DRAM which can affect data retention time. The first leakage component is cell transistor leakage. Cell transistor leakage in DRAM is primarily attributed to “gate induced drain leakage” (GIDL) (Fig.1 (b)), which is a type of leakage caused by a high electric field effect in the drain junction. Negative gate bias creates a depletion region (N+ drain region) underneath the gate. This depletion region in turn creates an enhanced electric field in the region, and band bending caused by this field leads to band-to-band tunneling (BTBT) [2]. Electrons and minority carriers that migrate under the gate can tunnel into the drain, creating unwanted leakage current.

The second DRAM leakage component is dielectric leakage between the bit line contact (BLC) and the storage node contact (SNC) (Fig.1 (c)). Dielectric leakage typically happens within the capacitor itself, with electrons flowing across the metal and dielectric regions (Fig.1 (d)). Dielectric leakage is caused by electrons tunneling from one electrode to another electrode through the dielectric layer. This problem has recently become more acute in BLC and SNC, since the distance between the BLC and the SNC is shrinking due to technology node scaling. Dielectric leakage across the bit line and storage node contacts can also be negatively impacted by process variation in the fabrication of these structural elements.

SEMulator3D, a virtual fabrication platform, can be used to build a 3D device model of a DRAM using design and process flow data. After “virtual” fabrication of the device, leakage paths can be visualized in any direction within the SEMulator3D viewer, and total leakage values can also be calculated and exported. This capability is quite useful in understanding the effect of process changes on DRAM leakage current. A Drift/Diffusion Solver in SEMulator3D provides IV analysis including GIDL and junction leakage calculations, to enable integrated design technology co-optimization. Users can see leakage values as they make changes in the structure, doping concentration and bias variation of their design.

Fig. 2 (a) IV curve change at V_G negative swing by V_D variation, (b) IV curve change by gate oxide thickness variation (+/-1nm)

For example, Fig. 2 highlights an increase in GIDL as the gate oxide thickness is varied. A thinner gate oxide results in a higher potential between the gate and the drain of the modeled device.

Fig. 3 (a) & (b) Leakage between BLC and SNC w/wo BLC residue, (c) leakage current change by voltage sweep

Fig. 3 illustrates the dielectric leakage path and the total current difference between the bit line and storage node contacts in SEMulator3D, highlighting the effect of BLC manufacturing variation during the etch process. The total leakage current of a structure with BLC residue (due to process variation) is higher than that of a structure without the BLC residue, as illustrated in Fig. 3 (c).

Fig. 4 (a) DRAM capacitor Z-cut image and dielectric leakage path, (b) capacitor X-cut image and dielectric leakage path, (c) total leakage current change by applied bias variation

Fig. 4 displays an example of dielectric leakage across a DRAM capacitor. Figures 4(a) and 4(b) display a Z plane and X plane cutaway of the DRAM, with projected dielectric leakage paths readily visualized in the SEMulator3D device model. Fig. 4 (c) displays the leakage current change at the bottom layer (BTM) electrode, as a function of applied bias.

Fig. 5 (a) Doping concentration view of DRAM cell, displaying the types (and expected locations) of capacitance at WL2 and other nodes when an AC signal is applied to WL2, (b) Calculated capacitance values between WL2 and other nodes on the device

Another important factor that can affect DRAM performance is parasitic capacitance across the device. AC analysis should be undertaken in DRAM development, since bitline coupling can cause tWR (write recovery time) to degrade and create other faulty behavior. Capacitance measures must be considered across the device, because doped poly silicon is used not only in the transistor gate but also in the bitline contacts and storage node contacts, creating multiple potential sources of parasitic capacitance (see Fig. 5 (a)). SEMulator3D has built-in AC capabilities, to provide measurement of parasitic capacitance values across a complex simulated 3D structure. For example, SEMulator3D can be used to obtain the capacitance as a function of voltage between WL2 (the word line) and all the other nodes in a newly-design DRAM structure, by simulating the application of a small AC signal to WL2 (see Fig. 5 (b)).

In conclusion, there are multiple sources of leakage current and parasitic capacitance that can cause DRAM failures. These failure modes need to be carefully evaluated during DRAM development and should include the effect of process variations on leakage current and parasitic capacitance. DRAM next generation path-finding can be simplified by “virtually” building a 3D device using expected process flows and process variability, and subsequently analyzing parasitic and transistor effects under varying process conditions. SEMulator3D, with its integrated 3D process models, R/C analysis and device analysis, can quickly verify whether a proposed DRAM device structure is vulnerable to leakage current or parasitic capacitance failure under different process assumptions.

Reference
[1] M. T. Bohr, “Nanotechnology Goals and Challenges for Electronic Applications,” IEEE Trans. on Nanotechnology, 1, 1, 56-62 (2002)

[2] J. H. Chen, S. C. Wong, Y. H. Wang, “An analytical three terminal Band-to-Band tunneling model on GIDL in MOSFET,” IEEE Trans. on Electron devices, 48, 1400-1405 (2001)