IEDM: TSMC N3 Details

Hitting different power/performance/area points in the same process with variable numbers of fins.


I attended IEDM in San Francisco in December. There were two presentations about TSMC’s N3 process. This is actually a bit of a misnomer since TSMC has two N3 processes, one simply called N3. The other (the second generation) is called N3E. The two papers were:

  • Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond
  • A 3nm CMOS FinFlex Platform Technology with Enhanced Power Efficiency and Performance for Mobile SOC and High-Performance Computing Applications

N3 is TSMC’s last finFET node. N2 will be nanosheet technology (TSMC’s name for gate-all-around GAA technology).

The first paper covers N3, and the second (a late-news paper) covers N3E. You may have heard that N3 turned out to be challenging to yield, and the schedule slipped, but that’s not true. It was always scheduled for 2H 2022, which is a slightly longer development cycle than previous process nodes. It entered production on schedule last quarter, Q4. 2022. N3E should enter production in the second half of this year. There are two more N3 processes in the pipe. N3P is the third generation of N3, and N3X is optimized for HPC. As far as I know, nothing has been revealed about these processes other than the name. It is clear that N3E, once it is available later this year, will be the main N3 process, and N3 will not be used for designs beyond the initial tapeouts.

Here is TSMC’s official position from their recent earnings call:

  • Our N3 has successfully entered volume production in late fourth quarter 2022, as planned, with good yield. We expect a smooth ramp in 2023 driven by both HPC and smartphone applications. As our customers’ demand for N3 exceeds our ability to supply, we expect the N3 to be fully utilized in 2023. Sizable N3 revenue contribution, we expect to start in third quarter 2023, and N3 will contribute a mid-single-digit percentage of our total wafer revenue in 2023. We expect the N3 revenue in 2023 to be higher than the N5 revenue in its first year in 2020.
  • N3E will further extend our 3nm family with enhanced performance, power, and yield and offer complete platform support for both smartphone and HPC applications. Volume production for N3E is scheduled for the second half of 2023. Despite the ongoing inventory correction, we continue to observe a high level of customer engagement at both the N3 and N3E with a number of tape-outs more than 2x that of N5 in its first and second year.
  • Our 3nm technology is the most advanced semiconductor technology in both PPA and transistor technology. Thus, we expect customers to have a strong demand in 2023, 2024, 2025, and beyond for our 3nm technology and are confident that our 3nm family will be another large and long-lasting node for TSMC.

Somewhat surprisingly, the second-generation N3E is a more relaxed process than N3, presumably to improve yields and reduce costs by requiring fewer EUV layers. In particular, N3E has the same SRAM bit-cell size as the N5 family of nodes. To me, the big implication of this is that it makes no sense to put any large SRAM cache on the same die as a processor. Much better to use a cheaper N5 process to build the SRAM and then use advanced packaging to assemble the system. Since analog gains nothing from very advanced processes, I would not be surprised to see designs with a processor die in N3E, an SRAM die in N5, and an I/O die in either N5 or even N7, all either stacked or side-by-side in a system-in-package.

The N3 processes use what TSMC calls FINFLEX, which allows for variable numbers of fins to have different power/performance/area points in the same process. I covered this (and quite a bit more about N3) in my blog post reporting on OIP, TSMC OIP: FINFLEX, Analog Migration, mmWave, and Awards. The graph above comes from TSMC’s own blog post by Godfrey Cheng, TSMC FINFLEX – Ultimate Performance, Power Efficiency, Density and Flexibility, which takes a deeper dive. Most of the key numbers are in the above diagram.

I had planned to cover the two papers from IEDM in more detail. But, to be honest, since I am writing this over a month after IEDM, others have gone before me:

I recommend that you go and read all three of those posts.


On TSMC’s last earnings call, it said that there is available 7nm capacity. Of course, even if we are not in a recession, certainly some end markets are struggling. But there is also a possible issue with the most advanced nodes. Are there enough design teams and volume to keep the fab full once mobile and the other early adopters have moved on to the next node? I was talking to Handel Jones at some event recently, saying how I thought that more automotive manufacturers would follow Tesla’s lead and design their own chips. He said he thought it unlikely; it is both too expensive and too challenging for them to do. He thought most automotive manufacturers would have little option but to buy chips from the likes of Qualcomm and NVIDIA, even though that doesn’t give them differentiation. But if mobile and HPC will always want to be on the most advanced nodes, and automotive is not flooding in behind, then who is going to use all the 5nm capacity once the most advanced companies have moved on to 3nm? Especially as chips are more expensive per transistor in these advanced nodes, a further discouragement.

On the other hand, something similar to this gets said at each process node. As the old joke goes, the number of people predicting the end of Moore’s Law doubles every two years.


TSMC announced last year that N3 would be manufactured in Fab 18 in the Tainan Science Park. They recently also announced further investment in Fab 21 Phase 2. With my magic decoder ring, I can see that Fab 21 is in Arizona, and this expansion will be used to produce N3x wafers. This means Arizona will have both 5nm and 3nm, with 20,000 wafer-starts-per-month (wpm) in 5nm and 30,000 wpm in 3nm.


Earlier this week, Cadence announced that:

Global Unichip Corporation (GUC) successfully delivered an advanced HPC design and a CPU design using Cadence digital solutions. The HPC design was created using the Cadence Innovus Implementation System on TSMC’s advanced N3 process and featured a 3.5 million instance count that reached clock speeds of up to 3.16GHz. The CPU design was created using the AI-enabled Cadence Cerebrus Intelligent Chip Explorer and the digital full flow on the TSMC N5 process technology, delivering 8% reduced power and a 9% area improvement while significantly improving engineering productivity. 

Since this is a post about N3, let’s pull out another couple of sentences from the press release:

The Innovus Implementation System’s highly accurate GigaPlace engine provided GUC with support for TSMC FinFlex cell row placement and consideration for pin access throughout the flow for N3 design rule checking (DRC) closure. The state-of-the-art GigaOpt engine delivered improved optimization by enabling the most optimal configuration from the TSMC N3 library while balancing different cell row utilization. The Innovus Implementation System also includes a massively parallel architecture and incorporates the well-established NanoRoute engine, which enabled GUC to address signal integrity early in the design flow while improving post-route correlation. 

The key takeaway, I think, is that Innovus fully supports the flexibility that comes with the FinFLEX approach.

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