If These Chips Could Talk: Actionable Insights From Path Margin Monitors

One of the most important current trends in electronics is the gathering and analysis of big data to reap benefits in cost, power, performance, and reliability. This is becoming common in the chip development flow. For example, data harvested from simulation regressions can aid in debug and reaching coverage goals. Machine learning (ML) uses the results of many passes through implementation (logic synthesis and layout) tools to optimize the power, performance, and area (PPA) characteristics of a design. Data is now mined and leveraged at multiple points during the pre-silicon phase of a project, but until recently this process has stopped once the chips are fabricated. This is changing rapidly as designers add structures to silicon that provide feedback during chip bring up, production test, and deployment within end products in the field.

If chips could talk, what could they tell the companies that make them? For a start, the data might show that the chips can run at a reduced voltage while still achieving the same performance. This has clear and valuable benefits. Lower voltages put less stress on the silicon and may increase product life and reliability. Less power means lower costs to use end products, reduction in power generation and cooling, and less impact on the environment. Even more opportunities for power savings are available with the dynamic voltage and frequency scaling (DVFS) techniques used in system-on-chip (SoC) designs. The data analysis can provide valuable guidance on how to vary voltage and clock rates to optimize both performance and power in production use.

Feedback from the field may lead to better test patterns to improve quality in manufacturing or   more efficient binning of parts. The insights from the field and chip test may result in better failure prediction and long-term reliability. The data may provide benefits even further back in the development flow, improving design variants for future generations of chips. Parameterized field data from many chips enables more accurate circuit models that are better correlated with actual silicon. Chips can be designed with better DVFS capabilities and PPA optimization. There are indeed many opportunities to learn and improve using the information that chips “communicate.”

All these benefits can be obtained today by including path margin monitor (PMM) IP units in fabricated chips. PMM units provide fine-grained observability of silicon state non-intrusively while chips are operating in mission mode. They measure the delay of real functional paths without compromising the operation of mission logic. This makes them entirely complementary to ring oscillators and process, voltage, and temperature (PVT) monitors that measure environmental parameters versus structural parameters. Each PMM unit selects as its input a signal from functional paths. Selecting from a collection of nearby signals allows one PMM to be shared across multiple functional paths. These paths should have high toggle rates and either resemble critical paths or contain devices susceptible to degradation over time. The selected signal is latched into a shadow flip-flop and fed through a series of delay elements.

At each stage of the delay chain, the path margin is compared against the shadow flip-flop. After sequence of comparisons the margin can be determined by detecting the failure point of the capture flip-flop. Collecting measurements from many paths across the chip yields a comprehensive view of timing margin. Different areas of the chip may behave differently due to local hot spots, and measurements of a single path may vary over time due to voltage and temperature changes. Measurements across many chips show the effects of process variation. All this diverse data must be gathered in the field, collected in some sort of central hub, and analyzed intelligently to gain the sort of insights and optimizations mentioned earlier. Combining the path margin data with other categories of sensors, such as environmental or functional, opens up a realm of use cases.

The Synopsys SiliconMAX Silicon Lifecycle Management (SLM) platform has all the capabilities to provide a PMM solution. These include SiliconMAX Path Margin Monitor IP to measure timing margins for real paths in-test or in-field and Synopsys SiliconDash to perform analytics in the cloud and provide insights based on the data collected. This solution provides several features to automate the use of PMM IP and leverage it in chip development, test, and the field. During PMM insertion, the PMM units are placed systematically across the die to capture the state of the silicon precisely at a fine physical resolution. The flow also inserts a PMM controller to manage the configuration and data collection for multiple groups of PMM units and adds internal memory storage for configuration and results. The controller has a scan chain bridge, an IEEE 1500 interface for access during chip test, and an APB interface for in-field access.

There are enormous benefits to having greater visibility and insight into the operational margins within a chip. At advanced technology nodes the process variation between devices and across the die increases. In addition, aging is becoming a major reliability issue as wire resistance and transistor characteristics change over time. Insight into the silicon is the only way to monitor and track the effects of technology and aging on timing margins. The path margin monitor approach is a well-established method to maximize performance and minimize power based on the actual margins available. Synopsys provides a complete and proven PMM solution. All chip developers should ensure that their chips can talk and that they listen to what SiliconDash has to say.

For more information on the complete SiliconMAX SLM solution, a white paper is available.