Implementing ESD Protection In Today’s SoCs

As the semiconductor industry transitions to FinFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts.

Technology scaling
With technology scaling we are seeing shrinking design windows available for ESD engineers due to narrowing margins between the nominal voltages and device breakdown voltages. Snap-back devices such as GGNMOS and SCR clamps have very low parasitic and are often used in high-speed I/O, RF and critical analog circuits. With FinFETs, it is extremely challenging to design snap-back devices — if not impossible. The failure currents in these devices have reduced by 50%, prompting larger ESD devices, which in turn increases the parasitic capacitances and impacts the products’ performance. In addition, thinner interconnects increase the possibilities of wire self-heating, requiring significant layout changes from one process node to another. Looking at the common causes for ESD failures, almost 55% of the failures are interconnect-related and can be avoided by performing systematic ESD checks during design phase.

Fig. 1: Technology scaling.

Design trends
Today’s SoCs integrate several IPs such as analog, RF, memories, high-speed I/Os, and processor cores at the SoC level. Each IP that is integrated into the same silicon has different functional requirements, making ESD protection device reuse very challenging. For example, a high speed I/O such as DDR operating at more than 1.5 to 2GHz requires very low parasitic capacitance and different ESD protection compared to traditional I/O. Interface signals between IPs that traverse across power domains need to be protected from ESD discharge events. Similarly, power domains that connect directly to the C4 bumps need core clamps to protect them from discharge. So an ESD protection scheme that worked in one design cannot be re-used for another design or another process.

Fig. 2: Design trends.

Higher pin-count, thinner interconnects, gate-oxide, stringent constraints, and multiple power islands make the ESD protection network design challenging in the sub-16nm/FinFET era. Correct by construction approaches that worked in the past are no longer viable solutions, the lack of full-chip ESD verification solutions make the sign-off process for ESD integrity significantly difficult, and in many cases, impossible.

Given the complexity of today’s system-on-chip (SoC) designs, higher resistance of the power and ground meshes, increased device density, and the greater sensitivity of the metal and device structures to breakdown in the advanced technology nodes, the proper design and placement of ESD protection circuitry has become increasingly critical.  However, there is a clear lack of design and analysis tool suites especially at the full-chip level to ensure ESD integrity of the IC.

ANSYS PathFinder, a full-chip ESD integrity analysis and verification solution performs several different checks such as connectivity and current density, both at the IP and at the full-chip level, providing a unique verification environment to ensure ESD integrity for today’s advanced designs.

Stop by the ANSYS Booth (# 313) at the EOS/ESD show in Anaheim, California (Sep 12 – 14) to understand how using full-chip level modeling techniques ANSYS solution helps verify that a design meets ESD guidelines, and identifies “weak” areas of the design (layout or circuit) that are most vulnerable to ESD failures.