Improving Robustness And Minimizing Over-Pessimism In The Face of Rising Design Variability

Part 1 of this blog explored the problems facing designers working on Systems-on-a-Chip (SoCs) targeting energy-efficient design, and how Synopsys’ PrimeShield design robustness solution can help optimize designs for lower power while achieving aggressive time-to-market goals.

This last part will delve into how the PrimeShield design robustness solution can help SoC designers optimize their designs for high performance while meeting aggressive design schedules, as well as provide some real-world examples.

Design robustness for high-performance design

In the case of timing, proven approaches use static timing analysis (STA) to analyze each timing path and check them individually against the frequency metric. Due to the significant variability of advanced nodes, especially at low voltages, analysis of potential performance bottlenecks caused by high variability is highly desired. Statistical analysis that identifies these bottlenecks through statistical correlation of all critical paths can avoid over-compensation while improving design performance, power and area (PPA) metrics. A new PPA opportunity has emerged for timing performance as well.

The PrimeShield design variation analysis (DVA) computes accurate per-endpoint sigma by explicitly tracking the correlation among paths going through common cells. It enables predictable timing using STA Monte Carlo analysis with accurate timing data from existing LVF libraries and is highly optimized for runtime. DVA’s path correlation-aware approach significantly reduces pessimism versus the traditional methodology of assuming paths are independent. The variation robustness capability also identifies bottleneck cells across the chip, typically the cells with large variation and insufficient pin slack; fixing these cells can significantly improve design robustness with neglible power overhead.

In traditional methodologies based on timing margin, the increased margins intended to ensure robustness, negatively impact performance. The key to reducing timing margins is reducing the clock and signal skew redundancy by controlling the tracking between transistors over process variation along the clock path. To reduce timing pessimism, the PrimeShield design robustness solution performs a global skew analysis. The global skew analysis computes path robustness related to global and interconnect V_T skew.

Global V_T variations are strongly correlated within a single V_T class, but only partially correlated among different V_T classes. Applying both min/max timing deratings is too pessimistic as is the case with traditional analysis; however, the analysis of 2^N combinations for N V_T classes is extremely cost and resource intensive. As a result, designers are forced to use only one V_T type in their clock network saddled with the penalty of extra timing pessimism.

The PrimeShield global V_T skew analysis allows the user to apply the same derating to all cells of the same V_T class in both the launch and capture paths. It thus cancels out the launch/capture impact from variation in the same V_T class, significantly reducing pessimism while still ensuring signoff safety. This analysis also enables the use of more than one V_T class in the clock network, while improving signoff safety at the same time, even with one V_T type in the clock network.

Furthermore, the PrimeShield design robustness solution improves designer productivity by significantly cutting down the number of STA corner libraries needed for global V_T variation and also the 2^N V_T combination runs needed for the N V_T classes to determine the worst mixed V_T timing slack.

Similarly, the metal/interconnect variations are also highly correlated within each layer, but only partially correlated among different metal layers. Applying both min/max parasitic bounds is too pessimistic as is the case with traditional analysis; however, the analysis of 2^N combinations for N metal layers is extremely cost and resource intensive.

The PrimeShield global interconnect skew analysis explicitly models the cancelation of delay impacts from variations within the same metal layers in the launch and capture paths. It reduces the timing pessimism while still providing signoff safety; fast Monte Carlo based analysis can be employed for the highest accuracy. Comprehensive design variation and global skew analysis minimizes timing pessimism guard-bands and over-margins, delivering improved design performance and a boost to F_MAX.

Proof is in the pudding

With early partnerships and extensive collaboration, lighthouse customers have turned to the PrimeShield design robustness solution to leverage mutual technologies and know-how to improve advanced-node design robustness and achieve new levels of power and performance.

The PrimeShield design robustness solution has already proven its effectiveness in several customer deployments:

• A global semiconductor leader in mobile/5G, HPC and automotive has deployed PrimeShield on 4/3 nm ultra-low-power design tape-outs after seeing 6% total power reduction across multiple blocks.
• A large North American semiconductor leader has deployed PrimeShield design robustness solutionon 5/4 nm designs, demonstrating a 7% boost to F_MAX with design variation analysis, 13-to-1 V_T library corner and runtime reduction, and 120× Monte Carlo simulation performance improvement.
• A large mobile phone chip supplier in Asia was able to improve F_MAX by nearly 8% on their next-generation 5 nm high-performance CPU while maintaining the same power and area.
• A supplier was able to reduce dynamic power by 11% on a 5 nm SoC designed for a leading US HyperScaler by using the PrimeShield voltage slack analysis while maintaining timing.

Wrapping Up

Today, due to the cost and complexity of statistical robustness analysis, it is typically performed late in the design cycle or even as a post-mortem. But for leading-edge customers, robustness has become an essential design quality metric in addition to power, performance, and area. The PrimeShield design robustness solution’s fast and high-capacity robustness analysis engine means designers can finally optimize towards the best design performance, power, area, and robustness (PPA-R) throughout the design flow.

The PrimeShield design robustness solution is available within the Synopsys Fusion Design Platform and delivers designs with the least statistical robustness loss and best design PPA-R. It powers customer design teams with comprehensive global robustness, skew, and voltage slack analysis and optimization to tackle design vulnerability stemming from variations while maximizing energy efficiency and performance for next-generation designs.

To learn more about how PrimeShield design robustness solution can help your SoC development succeed, visit the Synopsys website.