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Innovative Strategies Are Improving Early Design Circuit Verification

Avoiding time-consuming and error-filled LVS on early, incomplete designs.

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Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and complex foundry decks, meeting planned tapeout deadlines in the quickest turnaround time (TAT) can be difficult. In an effort to minimize TAT, most design teams now use parallelized design flows, where various blocks are implemented in parallel with the full-chip design. These blocks, which consist of both internal and 3rd-party supplier intellectual property (IP), are frequently in different stages of completion during the verification cycle, as shown in figure 1.


Fig. 1: Parallel design flows often contain blocks in different stages of completion.

However, design teams typically can’t wait to run LVS verification until all the blocks are complete and implemented, for several reasons:

  • Merging completed blocks can result in numerous connectivity errors between the blocks
  • There is less time to debug errors near the end of the verification cycle, when tape-out deadlines are imminent
  • Fixing errors may require significant changes to the layout, which requires even more verification iterations

Unfortunately, that means designers typically end up spending a significant portion of their LVS verification cycle iterating on “dirty” or incomplete blocks, macros and chips. Since not all classes of errors are relevant in these early stages, running full-chip LVS creates false violations that can range from hundreds to thousands. Design teams know that executing full LVS sign-off runs in every iteration is overkill, not to mention time-consuming—LVS verification of dirty designs can sometimes span days to weeks, due solely to the immaturity of the chip. Running LVS sign-off flows on dirty designs not only requires significant runtime and computing resource usage, but debugging and fixing this many errors, most of which will turn out to be false, is both frustrating and counter-productive.

With innovative electronic design automation (EDA) tools, designers can now run targeted circuit verification and debugging on blocks, macros and chips in early design phases. For example, the Calibre nmLVS-Recon early verification tool from Mentor, a Siemens business enables design teams to apply targeted circuit verification that provides capabilities typically missing or difficult to implement in early design circuit verification:

  • Categorization: Focus on specific high-value categories of early design analysis
  • Prioritization: Address the most impactful LVS discrepancies first
  • Task Distribution: Enable multiple designers/teams to focus on different sets of design issues simultaneously
  • Partitioning: Split data for easier debugging and root cause analysis
  • Data Reuse: Incremental execution on existing database and disk files to reduce runtimes
  • Interactive approach: On-the-fly edits to verify resolution, consolidate fixes, and speed up the debugging cycle

Early design short isolation

Designers often spend a significant amount of time finding and debugging shorts. Power/ground (P/G) shorts can be very complex, sometimes taking days to completely fix and verify. This complexity is due in part to the fact that these large nets contain P/G grids spanning the entire design size and crossing many hierarchies, and also because there can be multiple sources of the shorts. In fact, our research shows designers spending up to, in some cases, 80% of their early-stage verification cycle on this one issue.

The Calibre nmLVS-Recon short isolation (SI) use model enables designers to focus on short isolation and short paths debugging. The tool automatically executes only those steps of selective connectivity extraction that are needed to construct the required paths for short isolation analysis, while discarding unneeded operations (e.g., electrical rule checking, LVS comparison), using the foundry-qualified Calibre process design kit (PDK) “as-is.” After short isolation execution, designers can also leverage the Calibre RVE interactive short isolation (ISI) functionality to execute on-the fly debugging and resolution of shorts [1].

Designers can select from and combine multiple options to further delineate those areas in the design that are of particular interest:

  • Layer-aware SI
  • Net-aware SI
  • Custom SI

Layer-aware SI

To reduce both runtime and debug time, designers sometimes partition their designs into smaller segments, and perform short isolation and debug runs segment by segment. Designers could try manually partitioning their layout by layer or by block, and initiating short isolation verification runs. However, manually partitioning a design is tedious and time-consuming, and trying to isolate shorts on the partitioned segment may lead to incorrect or false results.

Layer-aware functionality enables designers to automatically and efficiently segment their designs using multiple options, depending on their needs, by adding a single standard verification rule format (SVRF) command to the rule deck:

  • Layers of interest: Designers can select layers of interest, such as back end of line (BEOL) metal layers. Focusing on a specific set of layers reduces the amount of data being processed.
  • Layer grouping: Designers can segment the layers into metal layer groups, each containing a specified number of layers. For example, a designer could segment the layers into triplet groups, beginning with Metal1 through Metal3, then moving on to Metal4 through Metal6, and so on. In this approach, the focus is on sequential short isolation, moving from one group to the next.

These segmentation approaches result in faster SI iteration runtimes and significantly shorter debugging cycles. As shown in figure 2, running the Calibre nmLVS-Recon layer-aware SI technology on dirty designs during initial routing enabled design teams to complete significantly more SI iterations than LVS sign-off iterations. Selecting BEOL layers showed an increase of up to 10x, while using layer grouping returned up to a 30x increase.


Fig. 2: The layer-aware SI options enables significantly more short isolation iterations to be run in a day, compared to full LVS runs.

Net-aware SI

During short isolation runs, not all shorts are of equal priority. For example, designers consider P/G shorts most critical, because they are found in large P/G nets covering the entire design. P/G shorts can also impact other areas of verification, creating inaccuracies and large numbers of false violations that are cumbersome to analyze. For those reasons, many designers prefer to clean P/G shorts first, before progressing to other areas of physical and circuit verification. However, given design complexity, hierarchical dependencies, and per-path investigation, P/G shorts can take a long time to debug.

Designers now have a systematic methodology that allows them to prioritize and resolve high-impact top-level shorts (like P/G shorts) before focusing on less critical shorts. In addition to shorts prioritization, the Calibre nmLVS-Recon net-aware SI mode produces faster iterations, and enables teams to achieve an efficient task distribution in which different team members can investigate different net types for simultaneous short paths analysis (figure 3).


Fig. 3: The net-aware SI option lets different designers focus on specific types of short isolation and debugging.

Designers can combine the net-aware and layer-aware options in a single run to leverage the benefits of both modes. For instance, if a design team wants to focus on critical P/G shorts, they can use the net-aware and layer-aware SI options together to focus on isolating P/G shorts by specific layers. Once all the P/G shorts are fixed for all layers, they can move on to signal shorts analysis. The combined process might look something like this:

  1. Identify the layers constructing the P/G paths.
  2. Run layer-aware SI on P/G nets only, starting with a specific set of layers (pair by pair).
  3. Use Calibre RVE interactive SI functionality to quickly isolate the shorts.
  4. Clean the shorts, save the results, then move to another set of layers.
  5. Repeat the layer-aware SI verification to confirm the chosen layers are clean.
  6. Gradually progress through the remaining sets of P/G layers until all P/G shorts are fixed.
  7. Run net-aware SI to analyze signal nets.

Custom SI

The Calibre nmLVS-Recon tool also offers a full configurable short analysis for design teams that need a precise debug and extremely concise iterations. Suppose a design team wants to run a short analysis on particular nets of interest (e.g., finding shorts between PWR1 and GND1), rather than performing short isolation on all nets or all P/G nets. Using a custom query server TCL script as input to the Calibre nmLVS-Recon SI invocation, they can easily and quickly perform a customized short path analysis for more succinct results, based on their needs and priorities.

Database reuse

Another innovative means of reducing LVS runtimes during early design verification is the reuse of previously-generated LVS databases. Running SI verification incrementally on existing databases is faster simply because previously-executed steps, such as constructing the needed connectivity and other required operations, can be skipped entirely. These LVS databases can be generated from a previous full-chip LVS run, an extraction run, or a previous Calibre nmLVS-Recon SI run. Database reuse can be used with all of the Calibre nmLVS-Recon SI options to achieve faster and more focused short isolation.

Designers can use a previously-generated database (even if short isolation was not enabled) to perform a short isolation run for P/G shorts (figure 4). Once the P/G shorts are fixed, the designers can use the same database to perform a short isolation run for I/O shorts. Running the Calibre nmLVS-Recon SI options with previously-generated databases provides a simple, yet intuitive process flow, because once the data is available, designers can quickly run multiple iterations for faster debugging.


Fig. 4: Running short isolation on previously generated databases enables faster iterations.

Conclusion

Meeting today’s ever-stricter tapeout deadlines can be overwhelming in the face of large design sizes, multiple hierarchies, and complex rule decks. While LVS verification is an important and necessary component of design verification, early execution of the LVS sign-off flow in every iteration on dirty and incomplete designs is a time-consuming and inefficient task that results in designers chasing thousands of false LVS errors in search of the few true critical issues.

Using an early design verification tool that is targeted to specific early circuit verification issues and designed for fast runtimes can vastly improve turnaround time and productivity by resolving issues that substantially impede early design analysis.

The growing trend toward early design verification technologies helps semiconductor companies improve overall verification and debugging flows for today’s complex designs. With the relevant feedback available during early design verification, designers can prioritize high-value verification strategies to shorten their debug cycle and deliver designs on schedule.

To learn more, download our whitepaper “Increase LVS verification productivity in early design cycles”.

References
[1] Raghav Katoch, “Improving productivity with more efficient LVS debug,” Mentor, a Siemens Business. Sept. 2019. https://go.mentor.com/58RHi



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