Integrating Embedded FPGA Made Easy

Chip designers have been integrating hard and soft IPs for decades – some being easy to integrate and others much more difficult. But what about eFPGA? It’s a relatively new IP on the IP landscape and according to data from Gartner, the market share of semiconductors with eFPGA is expected to approach $10B in 2023 with greater than 50% compounded annual growth. So, this raises the question for designers and back-end engineers considering using eFPGA IP for the first time: how easy is it to integrate and how do I test it?

At Flex Logix, this was a number one concern for us for two reasons: First, we wanted our customers to have a positive experience (repeat business is essential for a strong IP business – which we are seeing with multiple customers). Second, we envisioned eFPGA as being as ubiquitous as embedded CPUs over the coming years and needed to develop IP that was easily to integrate to support many, many customers with various eFPGA resource requirements efficiently. It also helps that our CEO, Geoff Tate, who was the founding CEO of Rambus, had worked through many of these issues as he built a successful company around licensing hard IP for various processes.

In particular, here are few of the product architecture choices we made with EFLX to make it easy for our customer to integrate.

• Metal Stacks: Most complex hard IPs typically support one or two metal stacks for a particular process. One of the benefits of our XFLX patented interconnect is that it allows us to use fewer layers of metal and enables compatibility with more foundry offered metal stacks. The benefit to our customers is more freedom to choose the metal stack that will give them the broadest choice of IPs to use for their chip.
• IR Drop: We run timing closure of our IP at SS/TT/FF and -40 to 125C and voltage as specified by the foundry process along with EMIR at worst case conditions. This translates into the backend design team not having to worry about IR drop (and performance impacts). That way, we guarantee the timing of a design in silicon to be within a few percentages of what is predicted by the compiler.
• Timing Closure: The inputs and outputs of the EFLX eFPGA are flopped which allows timing isolation between the SoC and eFPGA fabric. Customers use the provided .lib to close SoC timing like any other hard IP. Unregistered inputs can also be supported, but the designer will need to factor in input timing delays as part of the timing closure effort.
• Simulation: Gate level simulations models and test benches are standard deliverables and can be used with commonly used simulators such as VCS, Xcellium, Questa/ModelSim, etc. Verilog models are also generated by our compiler which can be used for simulation as well. The provided models support simulating programming the EFLX eFPGA, or for faster simulations, the models can be pre-loaded with the design configuration bits. Emulation models are also available for Veloce and Palladium.
• DFT Testing: The wrapper that connects the EFLX DFT port to the SoC scan chain supports fast, parallel loading of test vectors and parallel testing of EFLX eFPGA tiles. DFT coverage is 97+% of stuck-at faults plus~2% in functional test coverage when the DFT vectors are being loaded to give an effective test coverage of ~99%.
• Loading the bitstream: We provide a wrapper that connects our configurable programming port to internal buses such as AXI, AHB, JTAG and QSPI to make it easy to connect the programming port to whatever on-chip bus is available.
• Dynamic Re-programmability: The EFLX eFPGA can be reprogrammed without powering down and re-booting the chip by putting the eFPGA into reset mode and loading a new bitstream. Configuring a single EFLX core ranges from 482 us to 1.64 ms but can be improved to <17 us for very fast dynamic reconfigurability needs which can be demonstrated on our InferX X1 Inferencing co-processor.

All the above are nice features and benefits of our IP. But what really matters is, is it easy to integrate? To answer that question, I cite our quickest customer tape-out, which was two and a half months from IP delivery on a finFET process. (And, in case you’re wondering, the silicon worked the first time.) That’s easy to integrate!