Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators.
By Gary Ruggles, Sr. Product Marketing Manager, Synopsys
Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a Host and Device is required. A consortium to enable this new standard was recently announced simultaneously with the release of the CXL 1.0 specification. This article describes some of the key features of CXL that system-on-chip (SoC) designers need to understand in order to determine the best use and implementation of this new interconnect technology into their designs for AI, machine learning, and cloud computing applications.
PCI Express (PCIe) has been around for many years, and the recently completed version of the PCIe base specification 5.0 now enables interconnection of CPUs and peripherals at speeds up to 32GT/s. However, in an environment with large shared memory pools and many devices requiring high bandwidth, PCIe has some limitations. PCIe doesn’t specify mechanisms to support coherency and can’t efficiently manage isolated pools of memory as each PCIe hierarchy shares a single 64-bit address space. In addition, the latency for PCIe links can be too high to efficiently manage shared memory across multiple devices in a system.
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