IP Integration Challenges Increase

Semiconductor Engineering sat down with Chris Rowen, CTO of Cadence‘s IP group; Rob Aitken, an ARM fellow; Patrick Soheili, vice president of product management and corporate development at eSilicon; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at Synopsys; and Kurt Shuler, vice president of marketing at Arteris. What follows are excerpts of that conversation.

SE: The amount of IP in SoCs is increasing, and the blocks themselves are getting larger and more complex. What effect is this having on integrating them into chips?

Rowen: It’s certainly true that the overall complexity of chips is going up more than linearly in the transistor counts because the number of potential interactions between the blocks is going up and the amount of software is going up. That all mixes together to make the problem more difficult. On the other hand, the level of quality of the IP, the level of integration of the IP, the support of standard interfaces, the scale of the IP blocks are also going up. There are more and better tools available for this IP integration process—more simulation, modeling, performance analysis, power analysis, projection of size, and support of software at different points along the way. It’s now routine that people bring up and run full chips before they ever tape out. And they’re doing it in models, emulators, FPGA boards. They’re using a whole variety of tools that have been built around this hardware-software integration problem. The IP is better, it’s bigger so it assumes a broader range of functions than it did previously, and the tools are better. At least there’s hope of being able to keep up with the daunting challenge. But it’s a hard problem.

Aitken: It is getting harder. Part of the reason it can become easier is that IP providers are being required to do more characterization and more prototyping. We spend a fair amount of effort with new cores, building them, putting them on test chips on advanced nodes, keeping track of how the tools interact with them. There’s another aspect to it, though, which is down at the low level guts of all this stuff. As we move to these new nodes there are a bunch of electrical challenges we need to cover. Part of the IP characterization is additional characterization that happens on the SRAM instances, the additional care that goes into standard cell design, and other things to make sure those LEGO blocks don’t break the rest of the system when you integrate them. There’s a bunch of stuff that’s been hidden within the IP provider to make the overall integration easier.

SE: Is that only for the most advanced nodes, or is it at established nodes, too?

Aitken: It happens at established nodes, too, but it’s mostly focused on the advanced nodes because that’s where people are running into these kinds of problems. So you can re-characterize a library at 180nm, but it’s not going to show the same things you’ll see at 14nm and 16nm.

Shuler: The thing that is getting more people in trouble is the integration of different IP. So it may be 80% commercial IP, 20% in-house IP. There are different power management schemes. Each IP vendor has different ways of doing it. Companies seem to have a lot of trouble with that, so as time goes on there need to be more tools and more modeling to characterize that. Monte Carlo is the functional modeling. One of our customers is doing performance modeling. Power modeling will be the next important thing. Another problem we’re seeing is that automotive is starting to move to 40nm and 28nm from 55nm. The reason is the complexity of the imaging requires that. But they also have environmental requirements for chips—vibration, heating and cooling. For us as a soft IP provider, that’s not a big issue. But for the companies making the hard IP and the tools, it will be a big issue.

Nandra: There’s an expectation from the customers that the vendors provide more stuff—more pieces of IP. This includes IP that needs to be qualified, standard or hard IP that fits into technology requirements. They’re also expecting the vendor to provide some sort of integration of that IP into a chip. Sometimes that means you have to integrate your own IP blocks together. So you may have a PCI Express subsystem or a audio/video subsystem that includes MIPI/HDMI. This piece of IP sits in a customer’s SoC and works without too many integration challenges. That’s how things are evolving. It also involves firmware and software bring-up, which becomes the onus of the IP vendor. That’s an expectation.

Soheili: When the market is rich with IP, we don’t build it unless optimization is required. We pass through all IP costs and NRE to our customers, and we make or break our bank when we ship our chips. If the chips don’t go to production, that’s when we pay for it. When you are doing FF (fast fast) and FS (fast slow) and everything is working and it all resembles the right piece of IP, there is still another layer beyond that involves implications for the rest of the chip.

SE: How does consolidation affect IP?

Rowen: The clear implication, at least in the immediate sense, is fewer but more sophisticated buyers. They’re already sophisticated buyers. But the bigger the company is, the more thoroughly the company understands what it is they’re trying to do. The teams are more focused. They have sophisticated methods for selecting and buying IP. It raises everyone’s game.

SE: Is that true across the board? There are big systems companies now making their own chips that didn’t really have much experience in this space before.

Rowen: Those guys are very sophisticated buyers of IP. They have acquired the talent. They rise to the stakes of the game. They are extremely thorough and they know exactly what’s at stake. They have a direct line to what is the difference in the ultimate end user marketplace between a successful and an unsuccessful product. It’s very clear for them. In that sense, they’re good buyers. They know what is at stake.

Nandra: They’re also good negotiators.

Aitken: They also can drive your roadmap. We had one company that was very new to the business. On the first visit there our rep talked to one person. On the next visit they talked to 10 people, and on the third visit there was a room full of people they were talking to, and they were all very good. These guys are hiring the talent they need.

Shuler: You can follow this trend, too. If you look at all of these people on LinkedIn every time there are layoffs and you can look at where they are these days you can plot the hiring.

Nandra: These companies are open to purchasing third-party IP, too. You’re no longer going into a group where you have make-versus-buy discussions. It’s more like, ‘What can you do to help us drive the road map?’ I agree there is sophistication. There also is leverage in negotiation, at which they are very skilled. But it also adds to the complexity of our business. We’re now talking about 7nm with some of our customers. They want to get to this conversation about memory compilers and standard cell libraries.

Aitken: I agree. With consolidation we will all collectively have to adapt to there being a smaller number of very powerful customers. It’s changing the ecosystem a little bit, not just for IP, but for foundries and EDA, and we will have to see how that affects us. But it’s also interesting in that it provides a little bit more direct contact with the people who eventually are using these things. Some of these companies sell actual end products and are now interacting with the ecosystem. It’s a new and interesting world.

Soheili: Chip production is the way we get paid, and this is really interesting because we’re one step closer to production. Some of these guys need to do commerce for these things. It’s very important to them—maybe less so in the cost or acquisition of their IP, but more so in the certainty of being able to go into production and have the kind of volumes and capacity that they need. So this is a good thing for the industry. One of the reasons the consolidation is happening is that there are monopolies that own their own hills and pounding their chests, and that puts pressure on the marketplace. How the marketplace reacts is by exiting the market or by consolidating amongst themselves. But what will come out of the consolidation of these companies? At the end of the day they want to get paid for their bold moves and the money they’ve borrowed and servicing their loans, and one big way to do it is to cut $2.5 billion out of the R&D budget. Was that all wasted money? Does it affect necessary IP? I worry about that.

Nandra: All of us are seeing a lot of RFQs coming in from automotive and IoT. But anything that requires ultra low power in mobile applications, there’s a ton of activity there, as well. Even in software, people used to be only interested in the upper levels of their stacks. Now they’re interested in what we do.

Rowen: This week is seems important to hang our heads and worry about the monotonic consolidation of the semiconductor industry, but history shows that is not the way it works. You may find there is a broad category of U.S.-based semiconductor companies that are in decline in terms of numbers, but there are also all these investments in innovation that are taking place in China and other parts of the world. There are all these system guys who have discovered that their value can best be achieved with custom silicon. So there are new sprouts. In a sense we had a forest fire of consolidation of the old-growth semiconductor companies. It cleared out the underbrush.

Aitken: There’s an opportunity or IP in that. The automotive industry is an example. If you look at the parts suppliers in the automotive industry, during the time that the car companies have consolidated the parts suppliers have expanded quite a bit. They are providing the same pieces into luxury brands and economy brands. The IP is in a similar situation. It is able to commoditize the R&D that would have taken place in multiple companies. Hopefully this is more than just servicing loans.