How SoC designers and integrators can effectively assess quality and completeness of soft IP cores.
This white paper focuses on how SoC designers and integrators can effectively assess the quality and completeness of soft IP cores. A methodology for accomplishing this goal is presented, and an overview is provided of the Atrenta IP Kit – an application of the SpyGlass platform that implements a soft IP quality qualification methodology.
To download this white paper, click here.
Disaggregation and the wind-down of Moore’s Law have changed everything.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Continued expansion in new and existing markets points to massive and sustained growth.
Aging equipment and rising demand are pushing up prices and slowing production.
Experts at the Table: Designing for context, and geopolitical impacts on a global supply chain.
Disaggregation and the wind-down of Moore’s Law have changed everything.
It depends on whom you ask, but there are advantages to both.
Research shows significant improvement in time to market and optimization of key metrics.
Efficiency is improving significantly, but the amount of data is growing faster.
Some designs focus on power, while others focus on sustainable performance, cost, or flexibility. But choosing the best option for an application based on benchmarks is becoming more difficult.
The clock network is complex, critical to performance, but often it’s treated as an afterthought. Getting this wrong can ruin your chip.
Moving forward will require a fundamental reconsideration of logic.
After years of research, chipmakers have started combining ultra low-power designs with advancements in harvesting technology.
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