Details the objectives of the IPSA standard and its approach, along with real-case examples highlighting the methodology.
This whitepaper is available from the IP Security Assurance (IPSA) Working Group that describes Accellera’s initial proposal to address the industry’s security concerns involving IP integration. Since integrators typically treat IP as a “black box,” vulnerabilities may inadvertently be inserted into an SoC/ASIC. The whitepaper details the objectives of the IPSA standard and its approach, along with real-case examples highlighting the methodology.
A System on Chip (SoC) or Application Specific Integrated Circuit (ASIC) is comprised of multiple components referred to as Intellectual Property (IP) blocks or just IP. These blocks come from multiple sources such as internal development teams, IP suppliers, tool-generated IP, etc. Typically, the SoC/ASIC owner integrates multiple IPs from multiple sources, which raises concerns about security risk. How much risk is the Silicon owner (i.e., Integrator) inheriting? What potential security concerns exist that the Integrator must address to ensure the security objectives of the SoC/ASIC are upheld? This paper introduces an emerging new standard called IP Security Assurance (IPSA) to address these concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to highlight IP assets and associated entries in the Common IP Security Concerns Enumeration (CIPSCE) knowledge base for the mitigation implementer to address.
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