Ivy Bridge Settles Old Bet

Think back seven years to 2005. Those were boom times with the housing market rising, the dollar high, 65nm node chips on the horizon and EUV the great future lithography hope. EUVL was late for the next (45nm) node, but a great new idea had appeared to fill the gap—water immersion scanning with 193nm exposure! But how far could wet 193nm lithography go before EUVL or some new thing, such as imprint, would overtake it? One thing was clear: The industry would find a way to keep up the two-year Moore’s Law pace, even if some manufacturing technology wasn’t “ready.”

It just seemed hard to believe that optical lithography could go much further. A 45nm “half pitch,” literally implied a full pitch of 90nm, which was disturbingly close to the absolute limit for water immersion. Of course, the actual minimum period on leading logic chips was three or four times the nominal node “HP” dimension, so the challenge was in process control, not physics. Still, it would only take two or three more nodes before real chips would challenge the fundamental pitch limit of water immersion. Was it worthwhile—or even possible—to try to keep doing 193nm immersion exposure at 32nm? What about 22nm?

Two industry veterans—Ken Rygler, President of Rygler & Associates, and Brian Grenon, proprietor of Grenon Consulting—embodied the industry disagreement. Both had wide experience in the photomask industry, Grenon at IBM and Rygler as the founder of Dupont Photomasks, and both knew the difficulties posed by old and new technologies. Grenon thought it was ludicrous to think that billions of circuit features could be successfully printed with dimensions that were one-ninth the exposure wavelength. Rygler figured engineers would find a way, even if he couldn’t imagine it just then.

So they made a bet on June 28, 2005: Grenon wagered $100 Canadian that when 22nm chips were shipped, their critical levels would not have been patterned using 193nm immersion lithography. Rygler took the other side, but offered 680 Chinese Renminbi—equal money in late June of 2005. I witnessed the bet, as did Wes Erck, then at Oasis Tooling, who agreed to settle disputes over details—like whether Imprint’s “Step-and-Flash” scheme was “optical lithography.” (Rygler continues to contend it is!)

Then the 45nm generation came, fabricated using 193nm exposure. Design restrictions became tighter and resolution enhancement techniques, more elaborate. Intel found that it could make circuits out of uniform unidirectional line-space gratings by cutting the (dark) lines to useful lengths in a second lithography step. That was the beginning of “double patterning” in high volume manufacturing.

Makers of NAND flash memories discovered that there was gold in fairly simple line-space arrays and NAND became a driver for lithography shrink. They implemented self-aligned double patterning with sidewall depositions and a trim exposure to break through the optical pitch limit. Once that was gone, flash memory would quickly get to 22nm or so—patterned with 193nm immersion and elaborate materials processing. But only flash memory can be easily done that way, at least until the design tools catch up.

EUVL wasn’t ready by the time the 32nm logic generation came, so 193nm immersion had to be combined with various RET and double patterning schemes. Computational lithography and fine tool control helped, but nothing was easy.

And then came Ivy Bridge from Intel, a true 22nm node technology, albeit with a relaxed pitch. Its 22nm FinFETS are being made with 193nm immersion lithography, not only for the gate gratings, but also for the fins and the cut-mask exposures—the really hard part! There must be a lot of post-development trickery involved, but the patterning step involves only 193nm immersion because, in 2012, that is the only technology that works at industrial scale!

So what happened with the bet? I e-mailed Wes, Ken and Brian when the first Ivy Bridge servers were installed. By June 19, Brian and Ken agreed that Ken had won, and would receive Brian’s $100 Canadian, which is worth 60% more in U.S. dollars than in 2005, with appropriate ceremony once Wes approved.

But, Brian wondered, would Ken go “double or nothing” on the success of EUV?

Ken declined, “I suspect, after the billions that have been poured down poured down the SXPL/EUV drain…that some use of it will come…but is one EUV tool per fab ‘success?’”

I wondered, would anyone bet on a node three generations out today? How will the 7nm generation chips be made? If I had to guess now, I would choose (sigh) 193nm immersion followed by self aligned quadruple or sextuple patterning (maybe self-assembled, maybe sidewall) for line-space gratings, with cut exposures via EUV and e-beam lithography. Does anyone have a better idea?