Things You Never Knew About System Verilog

Despite popular myths, not everyone learned software programming in college.


System Verilog is considered the current standard for a combined hardware description and verification language, and has been welcomed with open arms since it was approved by IEEE in 2005.

Its usefulness in designing and verifying new chips is well known among those who work with it. The only problem is that many engineers still don’t know how to use more than a fraction of its capabilities—and some still don’t know how to use it at all.

System-Level Design asked engineers who use System Verilog, as well as those who teach it at places like Denali, Mentor Graphics and Synopsys—the company that made it all possible when it donated OpenVera to IEEE. Here are some trends, problems and recommendations:

  1. The biggest challenge hardware engineers face is learning software constructs. This is the same problem that engineers face in working with TLM 2.0. Object-oriented constructs and concepts like inheritance don’t come naturally to engineers who have been working on hardware designs and verification their entire careers. They are natural extensions for younger engineers, however, who have been trained in both electrical engineering and computer science.

  2. In System Verilog, objects come and go on the screen, which can be extremely confusing for someone who doesn’t work with objects regularly. The hidden problem, though, is that when using graphical debugging tools, all the major simulators have their own version of IDE environments. If everything isn’t consistent, as in one vendor’s environment, you’re likely to see lots of dollar signs and print spools, says Joshua Filliator, who teaches a System Verilog course at Denali.

    There is work under way to fix this issue within Accellera, so that the verification environments share the same class libraries and ultimately will be able to use multiple simulators. (See related story on OVM vs. VMM) But until that happens, you’ll have to think in silos.

  3. Writing test benches in System Verilog can be done the same way as in Verilog, but you don’t get any of the benefits of System Verilog by doing that. System Verilog adds functional coverage—an understanding of how much of the design is covered—and it provides a lot of free code you don’t have to write.

“A lot of people are skeptical at first,” said Filliator. “You have to work with this stuff for awhile to see potentially how little code you really have to write to find a lot of bugs. And with System Verilog, you write the code once and don’t have to do it again.”

There is growing evidence of broader acceptance. All the major EDA vendors offer System Verilog courses—usually to capacity crowds—and there is a growing interest in System Verilog Assertions (SVA). But who exactly is taking these courses, what their background is and how effectively they use these tools is pure speculation.

–Ed Sperling