Changes Ahead In Low-Power Design

How quickly SoC blocks are powered down and up will become as important as how fast a processor can churn through 1’s and 0’s.

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One of the interesting things about low-power designs in ICs is just how effectively power-saving techniques are being designed into chips these days. At most of the larger chipmakers, and even at an increasing number of midsize fabless companies, the concepts for implementing low-power techniques are well understood, well tested and thoroughly familiar.

Two years ago, when the mainstream of design was at 65nm and in some cases 90nm, only the largest chipmakers had worked with multiple power island and multiple voltage rails. At 45nm, this has become standard practice, and the number of companies that are pushing into 45nm is growing as this node becomes mainstream.

The good news is a lot of work already has been done in these areas. The concepts of power intent are relatively well defined, even if there are two standards, and the verification of multiple modes and states and an understanding of how to turn off and on various power islands with the least energy are well tested. There has been much work in these areas.

The challenge, however, is getting companies that buy these chips to actually utilize all the power-saving features. Time-to-market pressures by OEMs have trumped power savings so far. Putting a chip into an end-user device and getting that system out the door is more important than saving a few minutes of battery life.

That will change over the next couple of process nodes as more features are added into devices and leakage forces most blocks to be in the “off” state when they’re not in use. At that point, wake-up time will have to be defined by OEMs because it will become increasingly critical to the user experience and the overall perception of performance.

There has been a tradeoff between power and performance four at least the past decade, but what will change is that the perception of overall performance will now include how fast power domains can be switched on and off rather than just how fast a processor runs. This is a significant shift, and it will do more to drive attention to low power designs than years of advancements in this area could ever achieve.