Low Power Drives Performance And TCO

By Pallab Chatterjee
A common theme at this year’s Custom Integrated Circuit Conference was the reduction of power and power management while increasing data throughput. Historically, the show has featured new techniques for ultra high accuracy and brute force improvements in performance at all costs. The main theme this year was that in a world of mobile endpoint devices, the goal is to get performance in a stringent low power envelope.

Highly attended sessions at the kickoff of the event were focused on 3D device interconnect, photonic interconnect, design and process interaction and energy efficiency from data center to handhelds. The systems shown operated up to 50Gb/s data rates and typically had less than 20mW/lane power dissipation. These designs were exploring the next generation in high-density connectivity for centralized compute applications.

The 3D and interconnect sessions reviewed the architectural and design aspects and considerations of creating mixed and stacked memory and logic systems, traditional stacked memory die with edge connects—with the results above 15 die in a stack, and the challenges of testability before and after the die are assembled. Some of the testing issues relate to the use of Known Good Die (KGD) in a pin-available die back-to-front stack vs. a hidden pin face-to-face configuration. A key point is the thermal management of these die stacks and care for power supply and multi-state power design to make sure that both die are available at the same time for data to be passed back and forth. As a new constraint, mechanical issues regarding the die stack have become part of the design flow.

There also was discussion about using photonic interconnects as a replacement technology for copper. The driver for this technology is an overwhelming reduction in power and reduction of energy loss through heat and signal degradation over voltage- or current-based signaling in copper. The photonic presentations featured systems operating down to 1.2v on a 0.13um process to produce 7.4Gbps results, as well as wavelength-division-multiplexed links in sub-65nm processes that had compensation for process and thermal-induced ring resonator mismatches. The session ended with a presentation of power-efficient I/O design that focused on active power reduction design techniques for single-rate symmetric systems.

The session on energy management covered the full power spectrum from large- scale systems through handheld devices. This is one of the first times the ecosystem for the hardware use models was discussed as a whole at an event, and in particular that the entire system hierarchy has common power constraints. At the large system level (data center, storage, computer servers) the issue is thermal management. Simple reduction in component power consumption does not necessarily reduce overall energy costs. A system of rule-based proactive policies has been created to identify operating cost issues and support a variety of thermal management techniques, including allowing the circuits to run at a higher temperature prior to cooling. Currently cooling costs exceed component operating power costs.

The continuation of the systematic design power reduction included wide dynamic range operation for near-threshold-voltage (NTV) designs. This technique allows for the larger scaling of operating power supply voltage, which results in a power reduction proportional to the square of the voltage. The use of FPGAs to access advanced process technologies with lower power characteristics was shown. These designs also can minimize power-hungry, high-current board-level I/Os and traces, while having multiple functions connected by low-power, on-chip interconnects. The results are custom implementations that support multi-task reconfigurable computing while providing high- performance computation for specific tasks.

Finally, the power supplies for the design, in a discussion of high-efficiency techniques for DC-DC converters was presented. Multi-power designs, including some systems with three or more supply voltages (5V, 3.3V, 1.8V, 1.5V, and 1.25V) dissipate a lot of wasted power in the step-down conversion of these supplies. High-efficiency fast transient DC-DC converters can help minimize these systemic power losses not associated with performance, but with the system architecture.

Outside of the CICC event, these techniques were utilized in new lower TCO systems. At the recent Oracle World event the new computer and storage systems have been released as “engineered systems.” The basis is a new processor design, which includes new memory and backplane design, tiered storage (DRAM, flash and disk) and connectivity access to a revised operating system and new applications. The “system” is designed and aware of overall power reduction, energy efficiency and reduced cost of operation. The recognition is that just component “sleep state” power reduction is not sufficient anymore for real applications, and that the use chain is now part of the design constraints.