Making Power Delivery Networks Better

Cost, packaging and mixed-signal content are the key considerations in low-power SoCs; plan ahead.

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Careful design of power delivery networks can make the difference in whether a chip manages power effectively or fails completely. This impact of cost and other factors in the design process has not gone unnoticed.

Aveek Sarkar, vice president of customer support and product engineering at Apache Design Solutions, pointed to the iPhone as an example, where 50% or more of the bill of materials is from semiconductor parts. “In the U.S. alone, 20 million such smart phones were sold in Q3 2010. Shaving even 10 or 20 cents off of the BOM adds up to millions of dollars. Thus there is a drive towards more integration, not only on the chip side but also on the package side. Package PDN design decisions, which include the number of layers dedicated to the package and the amount of decap that should be used, are critical decisions that affect the competitiveness of the part.”

Another consideration today is package design. “Package design is becoming a competitive differentiator. If you can make it very thin, if you can stack multiple die on top of each other so that you can cut down your communication time between the chips, your product will become highly differentiated. You also have to worry about cooling these 1+GHz processors in a hand-held device. These are critical product design decisions, but they have to be done in conjunction with the chip. It’s no longer, ‘I have this chip, what package do I look for?’ The SoC and package design has to go hand-in-hand especially when you are talking about 20 or 30 different domains in a 4-layer package,” Sarkar said.

Further, mixed signal content on the chip is another important consideration for power delivery network design. For SoC’s targeting mobile applications, one or more high-speed processor cores sits on the same piece of silicon as RF circuits. “When that digital processor switches, it can inject a lot of noise into the substrate, which acts like a resistive and capacitive network propagating that noise from the digital logic to the sensitive analog blocks,” Sarkar explained.

Finally, for advanced processes, there must be protection from ESD events. “An important consideration of an on-die power delivery network design is how to shunt the current injected into the PDN network during an ESD event quickly to the protection devices,” he added.

The best way to handle the issues: up front design planning, of course.

–Ann Steffora Mutschler