What to look for when sorting through the various levels of design for manufacturability, reliability and yield.
By Cheryl Ajluni
With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately.
Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, quality? Defined many different ways, its overall impact in today’s highly dynamic, highly competitive marketplace is clear. Quality designs breed successful products with a true competitive market advantage. Those lacking quality are set up for failure.
While quality has always been important in electronic design, device scaling is now making it all the more important to achieve and, all the more difficult to obtain. In 2000, Dr. Ali A. Iranmanesh, founder and chairman of the International Symposium on Quality Electronic Design (ISQED), explained the problem this way: “We have witnessed a phenomenal increase in the level of device scaling as well as in semiconductor manufacturing quality. This has enabled the industry to provide ever more complex electronic products. However, the advancement in semiconductor technology has drastically surpassed the progress in the capability and quality of EDA tools and design methodologies. The result is a fast-growing disparity between the available capability and what can be realized in design practice.”
After nine years, has much really changed? Not really. Disparity is still present, as are other pressing concerns. Vendors continue to struggle to gain the advantage of being first-to-market. Once there, they must be able to meet increasing demand with a reasonably stable supply of product. But with process geometries shrinking, ensuring good and reliable performance from complex system designs as well as economical yields becomes difficult at best. It requires the designer to play close attention to every aspect of the design process, including the design’s reliability, manufacturability and yield. If the design is unreliable, its overall quality will suffer. If it cannot be manufactured easily or correctly, or if there are too many defects caused by the interactions between the design and the manufacturing process, then yield will decrease and quality will suffer. With reliability, manufacturability and yield all intricately tied to quality, what’s the system designer to do?
Luckily, the EDA industry has not turned a blind eye to the situation. Over the years it has rolled out solutions specifically designed to help designers improve quality by dealing with issues related to a design’s manufacturability, reliability and yield. As a result, DFx technologies—Design-for-Manufacturability (DFM), Design-for-Reliability (DFR) and Design-for-Yield (DFY)—have now become common terms in the designer’s vernacular and are even finding their way into the earliest portions of the design cycle.
“As dimensions shrink below 65nm, the difficulty of manufacturing is forcing designers to reassess their physical designs, a method alternately referred to as DFM, DFY or DFR,” said Jean-Marie Brunet, product marketing director for Litho Friendly Design and DFM products at Mentor Graphics. “Interestingly, the same methods and tools actually affect both manufacturing yield and reliability because the goal is to remove or adjust layout patterns that are difficult to render in the manufacturing process, and therefore are most likely to cause failures either during factory test or when the product is in the field. DFM/DFY/DFR tools apply rules and models to predict which specific shapes in a layout will cause problems in manufacturing, rank them in importance and, in many cases, fix them automatically, for example, by widening or moving interconnect wires, doubling up on vias, or repositioning layout edges.”
Employing DFM, DFY and DFR technologies, and the capabilities they enable, is a key way in which today’s system designers can improve the quality of the electronic systems they design.
DFM technology helps optimize a design so that it is as easy and low cost as possible to manufacture. What started years ago as standalone DFM tools have now evolved into offerings that are more tightly integrated with physical implementation. TSMC’s Unified Design for Manufacturing (UDFM) architecture opened the door to this possibility by providing EDA flows with access to TSMC DFM foundry data. For 45nm and 40nm process nodes, the data is provided in a DFM Data Kit, which includes data for lithography pattern check, critical area analysis and chemical mechanical polishing.
Beyond 40nm, DFM data along with an exact copy of the production model that was used is provided in a DFM Design Kit. EDA tools use this data to help designers quickly identify and fix any potential manufacturing issues. Today, DFM solutions are available from a range of EDA vendors, including Mentor, Synopsys, Cadence, Magma and Micrologic.
DFY is considered by many to be a subset, or even a new generation, of DFM that evolved to address the declining yields in IC production stemming from increasingly complex semiconductor processes. With nanometer range process geometries, yield is a function of the chip layout as well as the defects from interactions between the chip design and the manufacturing process. Yield can therefore be increased by reducing the defects or changing the design to make it less susceptible to those defects. As an example, reducing the critical area in the design layout can enhance yield (Figure 1).
Figure 1. The PEYE-Critical Care Analysis (CAA) tool from Predictions Software enables critical area to be generated from GDSII or within a layout editor. In this example, the metal one layer of a SRAM cell has been modified to reduce the probability of shorts between metal one nodes. The changes result in a greater than 10 percent reduction in the likely number of faults.
Of course, DFY is not limited to the manufacturing process. Stratosphere Solutions offers a silicon-proven platform and modeling platform, StratoPro, to address parametric yield and performance issues during both design and manufacturing. These platforms work together to characterize, model and analyze the impact of variability on parametric yield and performance. Appropriate changes can then be made to the design to make it more tolerant to process imperfections and variations.
A critical part of DFY technology is yield analysis, which helps determine those parts of a design that are most likely to be incorrectly manufactured. Earlier this year, Synopsys launched a yield management product, Yield Explorer, designed to bring design information into yield analysis by linking all aspects of the design, manufacturing and test flows into a single data bank (Figure 2). Product engineering teams can use this solution to quickly find and perform root cause analysis on systematic yield limiters, thereby improving yield and minimizing design respins.
Figure 2. Yield Explorer is a design-centric yield management solution enabling fast, interactive analysis throughout the product cycle. It can, for example, easily correlate output from ATE test to wafer parametric data during fabrication and also correlate DRC flags or timing distribution during design.
Design for Reliability
DFR refers to the process of designing reliability into products to ensure customer expectations are met. System engineers use DFR methods (e.g., correct-by-construction) and tools to design complex systems having a specified reliability. Generally this process begins with establishment of the system’s reliability requirements. During system design, these requirements are allocated and designed into the various subsystems. Reliability models are developed which evaluate the relationships between the system’s various parts, assessing differences in design alternatives. Some of the analyses that may be performed include: thermal analysis, fault tree analysis, root cause analysis, and EM analysis. While these techniques may be effective, ultra deep submicron (UDSM) design environments will require another option.
One company claiming to have the answer to this challenge is Micrologic Design Automation. Last year, it introduced a nanometer range EDA tool, nanoRVInteractive, designed to interactively eliminate reliability issues during the early stage of physical design (Figure 3). As opposed to other solutions that verify blocks only after they have been designed, going back to correct the design as necessary, Micrologic’s approach provides a reliability check in the early design stage by creating what it calls a reliability-aware design environment. In this environment, nonRVInteractive automatically analyzes a design for reliability phenomenon like electromigration, self heat and voltage drop (IR Drop) during the construction of IC layout. Designers can then use the resulting analyses to quickly determine the severity of any reliability issues.
Figure 3. The nanoRVInteractive tool is designed for nanometer- range IC reliability verification.
Developing quality electronic systems does not occur accidently. Disparity between semiconductor technology and design tool capabilities, as well as issues caused by scaling only makes this goal more challenging. Quality depends in large part on the design itself and its influence on reliability, manufacturability and yield. Consequently, to achieve a high level of quality, today’s system designer must pay close attention to the design’s reliability, manufacturability and yield using tools based on DFx technologies. Information garnered by these tools provides critical data that can be used to change the design to avoid specific problems. Doing so will not only improve quality, but also shorten development time, minimize cost and enable faster time to market—providing today’s designers the competitive advantage they need to succeed in the marketplace.
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