Managing Power Without Impacting Design Intent

Examining a power-aware verification flow.


The good news is that there are many techniques available to optimize power in your design. The not-so-good news? Many of these power management techniques also create new complexities in the physical and functional behavior of electronic designs.

Fortunately, there’s more good news: implementing a power-aware verification methodology can help you verify power optimization without detracting from design intent. What’s more, the right methodology can also help you minimize late-cycle errors and shorten debugging cycles. Power-aware verification is an integral part of functional verification.

A reliable power-aware verification flow consists of these steps:

  • Step 0: Write and scrub the Common Power Format (CPF)/Unified Power Format (UPF) power intent.
    • Prior to simulation, you can conduct power-intent screening with a static checking tool to verify and debug large designs without test vectors.
    • You can also use a low-power verification application to verify design functionality with static and dynamic power optimization techniques. This step helps ensure that power intent is ready to be verified.
  • Step 1: Create a power-aware plan to verify power features.
    • You can organize your tests based on power feature and verification method.
    • An automated verification planning and management tool that uses a metric-driven verification methodology can help improve design quality as well as team productivity.
    • Once you’ve chosen a platform to verify each entry, you can cover as much of your test plan as you can using static or formal engines. This approach can help you mitigate the risks of incomplete dynamic test coverage.
  • Step 2: Use a low-power verification app to execute the formal aspects of your verification plan.
    • Choose an app that can automatically check design structure and behavior, power intent, as well as low-power design guidelines.
    • An app that can create a power-aware RTL model would also be useful for power-aware static and functional verification analyses.
  • Step 3: Create dynamic tests to complete the rest of your verification plan.
    • Ideally, you’ll want to make sure that all of your verification tests are power aware and can be used across different verification engines.
    • A tool that automates system-level, coverage-driven test development can save time and effort in verifying your design’s power management features.
  • Step 4: Execute your dynamic tests on engines that are best suited for each test type.
    • There are a variety of choices here, from compiled-code simulators (great for block-level tests) to emulation engines (ideal for “deep” tests) and rapid prototyping platforms (a good option for software developers).
  • Step 5: Bring together all of the metrics coverage reporting. Here, you can select a tool with a web dashboard that allows you to see and share data with other verification teams, easily track progress against your plan, and manage coverage.

After completing these steps, you should be at a normal cycle of debugging and fixing any problems. If you must make power-intent changes, simply repeat all of the tests to re-verify the change. In summary, having a sound power-aware verification methodology can help you minimize late-cycle errors and shorten debug cycles.

Leave a Reply

(Note: This name will be displayed publicly)