Manufacturing Bits: Aug. 21

World’s smallest transistor
The Karlsruhe Institute of Technology (KIT) has developed what researchers say is the world’s smallest transistor.

Researchers have devised a single-atom transistor. The transistor switches an electrical current via a single atom, which resides in a gel electrolyte. The device also works at room temperature.

While others have developed single-atom transistors, KIT took a different approach. For one thing, the transistor consists of metal, which, in turn, enables a low power consumption. In the device, there are two metallic contacts with a gap as wide as a single metal atom

Previously, KIT has developed a single-atom transistor, which resided in a liquid electrolyte. Now, KIT’s new transistor works in a solid electrolyte. “The gel electrolyte produced by gelling an aqueous silver electrolyte with pyrogenic silicon dioxide combines the advantages of a solid with the electrochemical properties of a liquid,” according to researchers.

The single-atom transistor that works in a gel electrolyte reaches the limit of miniaturization. (Photo: Group of Professor Thomas Schimmel/KIT)

In effect, the transistor switches current through the controlled reversible movement of a single atom. “By an electric control pulse, we position a single silver atom into this gap and close the circuit,” said Thomas Schimmel, a processor at KIT, in a statement. “When the silver atom is removed again, the circuit is interrupted.

This quantum electronics element enables switching energies smaller than those of conventional silicon technologies by a factor of 10,000,” Schimmel said.

Gene chips
Osaka University, The University of Tokyo, Kyoto University and Waseda University have developed a gene-based logic device technology called gene nanochips.

Researchers have devised a self-contained chip. The self-contained gene chip consists of an actuator, sensors and DNA-based components. The technology could one day lead to large-scale, integrated genetic circuits.

In theory, synthetic genetic circuits could program cells to perform various functions in medical applications. Gene chips can be made today, but there are challenges. They are relatively simple devices and are prone to crosstalk among the different circuits.

To enable more complex and better gene chips, researchers from Osaka University developed a DNA-based rectangular sheet measuring 90nm wide, 60nm deep and 2nm high. The sheet formed the basis of the gene chip. Then, they integrated the actuator and sensors onto a DNA origami-based nanochip. The nanochip also includes an enzyme, RNA polymerase (RNAP) and multiple target-gene substrates.

Then, they integrated reprogrammable logic gates in the structure, “so that the nanochip responds to water-in-oil droplets and computes their small RNA (miRNA) profiles, which demonstrates that the nanochip can function as a gene logic-chip,” according to researchers in the journal Nature Nanotechnology.

Integrated nanochip (left, Schematic illustration. right, Atomic force microscopy (AFM) image) (Credit: Hisashi Tadakuma / Osaka University)

In a statement, Hisashi Tadakuma, a researcher from Osaka University, said: “All factors necessary for transcription reactions are on this integrated nanochip, so environmental sensing, information computation, and product output can be completed at the single-chip level. In the near future, autonomous nanochips will be useful in maintaining the cell in the healthy state through controlling gene expression spatially and temporally.”

Monolithic 3D
At a recent event, Imec and Soitec demonstrated a sequential 3D front-end integration process.

Imec’s process, dubbed sequential-3D integration, stacks two transistor device layers on top of one another on a 300mm wafer. The two device layers are connected using a series of interconnects.

The biggest challenge of sequential-3D integration is the management of the fabrication thermal budget. The top device layer must be processed at low temperatures below 525°C.

For this, Imec demonstrated a junction-less top device layer featuring a low fabrication complexity, which does not require junction formation, channel doping and activation performed prior to layer transfer. The top-tier device was processed at a temperature below 525°C, achieving good device performance.

TEM cross-section of the 3D structure showing (left) stacked top and bottom tier devices with nanometric alignment,(center) 3D contacts to the bottom devices and (right) magnified top tier P and NMOS devices. (Source: Imec)

“Demonstrating a good performance of the top-tier device using a low temperature process is an important breakthrough in our aim to develop sequential 3D as a valid option to further increase power-performance-area-cost in advanced technology nodes beyond 5nm,” said Anne Vandooren, senior researcher at Imec, on the R&D organization’s site. “To realize this, we had to use very advanced technologies in some of the most critical process steps including back-end-of-line, contact, and gate stacks.”