Manufacturing Bits: March 27

Nanostructure printers
Using electron-beam lithography and reactive-ion etching techniques, Singapore’s Agency for Science, Technology and Research (A*STAR) has developed a new high-resolution color nanostructure printing system.

The printer enables nanostructures made from silicon. It prints tiny structures with a wide range of colors. In the future, researchers hope that nanostructure printers could move from the lab to a desktop device. The system could one day enable miniaturized displays, data storage and security prints for identifying counterfeits.

The printer uses a combination of e-beam lithography and etch. With the technologies, researchers produced tiny silicon disks. The disks were 130nm high on a 70nm silicon nitride layer. The nitride acts as an anti-reflective coating.

A schematic of a surface with tiny silicon nanostructures. (Source: A*STAR)

Joel Yang, a researcher from A*STAR, said: “We have been working on ultra-high resolution color printing for the past five years, and now we have solved the problem of limited color saturation.

“An important requirement for ideal color reflection is to meet Kerker conditions, where incident light excites magnetic and electric dipoles in a silicon particle in such a way that the particle scatters light entirely in one direction,” explained Yang. “In free space, the uniform surroundings of the particle allow Kerker conditions to be met. A substrate will generally break spatial symmetry, but if the substrate does not reflect, the situation is equivalent to light propagating through free space.”

MEMS etch
In a separate development, A*STAR has devised a new plasma etching process for microelectromechanical systems (MEMS).

A*STAR has developed a two-step plasma etching process, which produces vias with minimal dimensions down to 1.5 microns. It also enables smooth sidewalls with angles of around 70 degrees.

MEMS are used in many applications, but there are challenges in terms of creating vias with tapered sidewalls at five microns or less. One method, which uses sidewall polymerization, is problematic. In this method, the widths at the bottom of the vias shrink, according to A*STAR.

There are other methods. For example, one can transfer a photoresist profile into an etched layer. This limits the maximal depth of the vias, according to the organization.

In response, A*STAR has developed a new two-step process using an inductively-coupled plasma reactive ion etching tool. The first step modifies the photoresist profile. The profile is transformed from a vertical to a tapered profile using Ar/O2/CF4 plasma, according to researchers.

Tapered contact opening fabricated by new two-step plasma etching process. (© 2017 IEEE. Reprinted, with permission, from Ref 1, A*STAR)

Then, an oxide etching process with sidewall polymerization is conducted. This was performed in C4F8/H2-based plasma. “MEMS are following the general trend of miniaturization in electronics, with devices that are reducing in size from the tens of microns to one micron or less,” said Vladimir Bliznetsov, a researcher from A*STAR’s Institute of Microelectronics (IME). “But the techniques used to manufacture top metal contacts to devices with such microscopic dimensions are costly and unreliable.

“(At A*STAR), we combined two effects which are usually harmful during the etching process — accelerated corner sputtering and sidewall polymerization,” said Bliznetsov. “Precise control of sidewall angle has use in many applications, and we are now planning to fabricate functional magnetic memory cells, which require pillars of magnetic material with sidewalls having a specific angle.”

MacEtch
The Rochester Institute of Technology (RIT) has put a new twist on the inverse metal-assisted chemical etching, or I-MacEtch, process.

RIT has applied I-MacEtch to a III-V compound called indium-gallium-phosphide (InGaP). Applications include photonics, quantum computing, semiconductors and solar cells.

Etch, the process step that removes materials from the wafer to create the features of a device, is split into two categories—wet and dry. Wet etch uses liquid chemicals to remove materials. Dry etch, the bigger of the two markets, bombards ions on a surface as a means to remove materials.

I-MacEtch is not new. It is a wet process in which the etching takes place under the metal. The technology has been used for processing silicon. More recently, the industry is looking to apply the technology for a range of III-V elements.

Combining I-MacEtch with gold materials, RIT has devised a way to fabricate suspended InGaP nanofoils at tunable thicknesses. The etch rates for undoped, p-type, and n-type InGaP are ∼9.7, ∼8.7, and ∼8.8 nm/min, respectively, according to RIT.

The process has some advantages over traditional etch methods. “What is novel about our work is that for the first time we are looking at applying I-MacEtch processing to indium-gallium-phosphide materials. I-MacEtch is an alternative to two conventional approaches and is a technique that has been used in the field—but the materials that have been explored are fairly limited,” said Parsian Mohseni, assistant professor of microsystems engineering in RIT’s Kate Gleason College of Engineering.

“We are using a simple benchtop set up and we end up with very similar structures; in fact, one can argue that they are higher in quality than the structures that we can generate with RIE for a fraction of the cost and with less time, less steps throughout, without the higher temperature conditions or expensive instrumentation,” Mohseni said.