Manufacturing Bits: March 4

Shrimp cocktail manufacturing

Harvard’s Wyss Institute has devised a new degradable bioplastic material, which was isolated from shrimp shells. The shrimp shell-based material could be used in the large-scale manufacturing of cell phones, food containers, toys and many other products. The material is also superior to most bioplastics on the market today. It could be used in place of existing non-degradable plastics.

Researchers made a series of chess pieces made from this material, dubbed chitosan, which is a form of chitin. Chitin, the most abundant organic compound on earth after cellulose, is a long-chain polysaccharide material. It exhibits some remarkable mechanical properties. It is the main component of the cell walls of fungi as well as the exoskeletons of crabs, lobsters, shrimps and insects.

The Wyss Institute researchers molded a series of chess pieces made of their chitosan bioplastic, demonstrating a new way towards mass-manufacturing large 3D objects with complex shapes made of fully compostable materials. (Source: Harvard)

Chitin has not been used in manufacturing, however. Researchers devised a scalable manufacturing technology for the production of 3D objects based on chitosan.

Researchers have characterized the mechanical properties of chitosan on a molecular level. They also devised a method that produced a pliable liquid crystal material, which could be used in casting and injection molding. Researchers also found a way to combat the problem of shrinkage. The chitosan polymer fails to maintain its original shape after the injection molding process. Adding wood flour solved the problem, according to researchers.

“There is an urgent need in many industries for sustainable materials that can be mass produced,” said Don Ingber, a professor of bioengineering at the Harvard School of Engineering and Applied Sciences, in the university’s Web site. “Our scalable manufacturing method shows that chitosan, which is readily available and inexpensive, can serve as a viable bioplastic that could potentially be used instead of conventional plastics for numerous industrial applications.”

More quantum well finFETs

Quantum well finFETs are a viable transistor candidate for the 7nm or 5nm node. In many respects, a quantum well finFET is a next-generation III-V finFET. In quantum well finFETs, a well is built in the device to confine the carriers.

In one effort, the Massachusetts Institute of Technology (MIT) has developed a new III-V, self-aligned quantum-well MOSFET architecture. MIT has demonstrated a 70nm gate-length InAs MOSFET. Devices with a ledge length of 70nm yielded a record ON-current of 410 μA/μm.

The heart of this device is a wet-etch free gate recess process that provides control over the vertical and lateral dimensions of the recess. This takes place in three steps. The first step is time-controlled reactive ion etch (RIE) of the W/Mo sidewall.

Then the n+ cap is removed by a low power Cl2-based anisotropic RIE. This is instead of using the common peroxide-based wet etch process. The final step is a digital etch that separates the etch chemistry into its two components–surface oxidation (in O2 plasma) and oxide removal (in H2SO4).

Meanwhile, in a separate effort, Sematech, the University of Texas-Austin, CNSE, TEL and GlobalFoundries rolled out a tri-gate, sub-100nm InGaAs quantum-well MOSFET. The proposed architecture marries tri-gate transistors and III-V materials. InGaAs channel materials are a candidate for low-power logic applications. Tri-gate transistors have been demonstrated in silicon-based MOSFETs.

“However, most of the III-V tri-gate devices reported so far have shown wide fin geometry or poor interface quality between high-k dielectric and sidewall of etched fin, failing to demonstrate performance and electrostatics benefit over the best ultrathin-body (UTB) planar III-V quantum-well MOSFETs,” according to researchers.

To boost the electrostatics, researchers devised a tri-gate quantum-well MOSFET. The device had a gate length of 60nm, a fin width of 30nm, a fin height of 20nm and an EOT of <1nm.

It also incorporated a bi-layer of high-k dielectrics based on Al2O3/HfO2 materials. All told, the device demonstrated a performance of 77 mV/dec. “This result is significant because it shows that excellent electrostatics and performance can be achieved with high-k oxides directly on an etched tri-gate MOSFET down to Lg=60nm,” according to researchers.

Masking the data

Aselta, a supplier of data preparation software solutions, has announced a partnership with Mapper Lithography. Under the plan, Aselta will offer a data preparation solution for Mapper’s FLX:1200, a multi-beam electron-beam system. The solution will enable a data preparation flow from the 90nm to the 14nm nodes.

The software flow features proximity effect correction, a simulation and analysis capability and a model-based verification engine. A complete FLX:1200 emulator has been implemented in order to mimic the pixelated data handling through the full data path. A new and so-called SmartBoundary scheme is adapted to Mapper’s data format to minimize alignment and stitching errors.

“We have looked at Aselta technology, and believe the Inscale software solution does a good job performing the necessary data prep task before feeding design data into our machine,” said Marco Wieland, Mapper’s chief technology officer, on Aselta’s Web site.