Manufacturing Bits: May 26

7-level nanosheets
The 2020 Symposia on VLSI Technology & Circuits for the first time will be held as a virtual conference.

The event, to be held from June 15-18, is organized around the theme “The Next 40 Years of VLSI for Ubiquitous Intelligence.” Among the papers at the event include advanced nanosheet transistors, 3D stacked memory devices and even an artificial iris.

At the event, CEA-Leti-Minatec is expected to present a paper on the first seven-level stacked nanosheet transistor FET. This in turn demonstrates a nanosheet FET could be extended for several generations.

Eventually, today’s finFET transistors will stop scaling, prompting chipmakers to move to a new transistor type, namely gate-all-around field-effect transistors (FETs). One type of gate-all-around FET is called a nanosheet FET, which are expected to appear at the 3nm node in 2022 or sooner.

An evolution of a finFET, a nanosheet FET is basically a finFET on its side with a gate wrapped around it. A nanosheet consists of several separate and thin horizontal pieces or sheets, which are vertically stacked. Each sheet makes up a channel.

A gate surrounds each sheet, creating a gate-all-around transistor. Generally, most nanosheet presentations involve technologies with three or four nanosheets.

Meanwhile, CEA-Leti-Minatec will demonstrate for the first time a nanosheet with seven sheets, according to an abstract from the paper. The nanosheet FET from the R&D organization has implemented a replacement metal gate process, inner spacer and self-aligned contacts.

In the paper, researchers will evaluate the trade-off of increasing the Weff/footprint to boost device performance with process complexity. They will demonstrate gate controllability with a high current drivability (3mA/µm at VDD=1V) and a 3X improvement in drain current over the usual two-level stacked nanosheet transistors, according to the abstract.

Next-gen HBMs
At the event, TSMC is expected to reveal a new low-temperature bonding and stacking technology for high-bandwidth memory (HBM).

Using the technology, TSMC will demonstrate 12- and 16-high die HBM stacks with better performance than the current techniques, according to an abstract from the paper.

In HBM, DRAM dies are stacked on top of each other to boost the memory bandwidth in systems. Each die has tiny microbumps. The bumps are connected using thermo compression bonding. The dies communicate with the base die using through-silicon vias (TSVs).

TSMC, meanwhile, is working on a technology called System on Integrated Chips (SoIC). SoIC utilizes advanced chip stacking techniques, enabling customers to develop 3D-like architectures. The stacking techniques is done using a copper hybrid bonding technology, which can bond two wafers together or a chip to a wafer. TSMC calls this SoIC bonding.

Nonetheless, using the technology, the company has developed 12- and 16-high die stacks for HBM with small form factors. A 12-high structure could have a total height below 600µm. The height can be adjusted to fit the requirements, according to TSMC.

The 12-high stacked structure incorporates more than 10,000 TSVs, according to the abstract. The bonds were tested. Linear I-V curves were obtained, demonstrating good bonding and stacking quality.

Compared to traditional microbump technology, the bandwidth for the 12- and 16-high die structures using SoIC technology shows an improvement of 18% and 20%, respectively, according to the abstract. The power efficiency for the 12- and 16-high die structures demonstrates an improvement of 8% and 15%, respectively. Also, the thermal performance for the 12- and 16-high SoIC-bond structures are improved by 7% and 8%, respectively, according to TSMC.

More papers
Many others will present papers at the event. On the biotech front, Imec, Ghent University and KU Leuven will present a paper on a fully encapsulated artificial iris. The iris is embedded in a smart contact lens.

The technology is designed to mitigate problems associate with human eye iris deficiencies. “The variable iris aperture is implemented using four concentric rings of varying diameter on an embedded lens LCD,” according to an abstract. “To operate for an entire day without having to charge the embedded power source, the system power consumption is 1.9mW to control the iris aperture as well as operate the 16 eye blink sensor, light sensor, and corresponding compute logic.”

On the memory side, meanwhile, Macronix International will present a paper on a scaled hemi-cylindrical (HC) 3D NAND device with a large memory window. The proposed cell area (0.009µm2/layer) is only ~32% of the standard 3D NAND cell area, according to the abstract. It enables a large >10V Vt memory window with 100K endurance.

In a separate paper, the University of Tokyo has integrated ReRAM arrays with indium-gallium-zinc-oxide (IGZO) access transistors monolithically in a 3D stack. With the technology, researchers have demonstrated basic functionality of in-memory computing in a 3D neural net.

In another paper, Kioxia will present its findings on a surrounding gate vertical-channel FET. The structure has a gate length of 40nm using a backend-of-line (BEOL) process compatible novel oxide semiconductor In-Al-Zn-O as a channel material. “Fabricated FETs exhibit high scalability by excellent thermal stability (~420°C) compared to conventional In-Ga-Zn-O-channel FETs, with high mobility (12.7cm2/Vs) characteristics,” according to the abstract. “Furthermore, the vertical-channel FET also exhibits excellent reliability and stable operation without a floating body effect. Endurance of more than 1011 cycles is also demonstrated. This work opens a pathway to realization of a high-performance BEOL transistor for 3D-LSI applications.”