Massively Parallel System-Level Testing

Decades of advances in the semiconductor industry continue to drive an insatiable consumer demand for smaller, more powerful, more ubiquitous devices – whether in our cars, on our countertops or around our wrists. To meet this demand now and into the future, the fabrication of increasingly complex semiconductor systems for an incredible spectrum of applications must scale accordingly. Additionally, standards of quality control need to exceed current levels due to safety-critical applications and brand perception. Likewise, testing methodologies must evolve to address this emerging complexity and comprehensively evaluate devices under test (DUTs) for defects that appear in real-world conditions. Finally, they need to achieve the desired product yields with minimal impact in terms of time and cost. As the industry moves toward higher-volume fabrication of ever more intricate systems and zero-defect shipments, it has to create a new paradigm for quality control that also satisfies manufacturing needs. That paradigm is massively parallel system-level testing (SLT).

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