Material Effects: Trading Performance For Power

By Ann Steffora Mutschler
Power impacts everything, even when it comes to semiconductor manufacturing materials. While bulk CMOS technology still reigns supreme, there are a number of advanced materials being suggested as replacements when it runs out of steam at around 15nm, including silicon on insulator (SOI)—particularly in combination with FinFET multigate structures on SOI—silicon germanium, gallium nitride, and aluminum nitride.

Most promising is SOI, already in use by IBM and AMD, which uses a layered silicon-insulator-silicon substrate instead of conventional silicon substrates to reduce parasitic effects and improve performance. Specifically, SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide, offering improved performance and diminished short channel effects in microelectronics devices. SOI can be implemented in two forms: partially depleted and fully depleted.

Jamil Kawa, group director of R&D in Synopsys’ implementation group, emphasized that SOI is not new. “It has been with us for a long, long time. It has a lot of proven benefits, yet it never became mainstream.”

He explained that SOI could be compared to bulk CMOS by a rule of thumb: you can buy either a node in power for the same speed, or a node in performance for the same power. For example, comparing 90nm SOI to 90nm bulk, if they are running at the same clock frequency, the 90nm SOI will have the lower leakage characteristics of the 120nm bulk. Another way of looking at it is if the SOI is operating at 90nm with the same power budget that a bulk is allowed to consume, then it can give the performance that the next-generation (65nm bulk, in this example) will provide.

While it appears to be a simple formula that is carried from node to node to node, SOI didn’t it catch fire as everybody thought it would mainly because of cost. “Given the lack of wide-scale adoption, the cost of initial wafers was more expensive and cost is extremely sensitive in our industry,” he explained.

SOI chip. Source: IBM

A second obstacle to SOI adoption has been the history effect inherent in the technology. There is no substrate with SOI. It is oxide. Therefore, charge accumulates and has nowhere to go, and this alters the behavior of the device over time. Guardbanding is used to get around the history effect. “If you want to go conservative by guardbanding 15%, all the advantages in speed that you got by going SOI you’ve given up by going conservative. There are techniques to alleviate that, but bulk has remained the easy way out, a proven technology, cheaper, with a lot of momentum in terms of history of use,” Kawa noted.

SOI is gaining renewed interest, however. At 20nm and 15nm, CMOS leakage is a big problem.

FinFETs are being looked at, sometimes in combination with SOI, as well. “At 15nm, you don’t have too many choices. Bulk is more or less dead. If you insist on going with planar, you go the SOI way. Or you go the FinFET way. There is also a third variation, which will most likely gain hold, which is FinFET on SOI. Nothing is ruled in or out yet, but the excessive variability of bulk at extremely advanced nodes is giving a second life to SOI. The verdict is still out so I’m not advocating one course or the other, but the move toward FinFETs on bulk or FinFET on SOI is clearly the way to go in terms of leakage control,” Kawa added.

Material effects on tools
While it might not seem obvious, the choice of process can affect EDA tool development to some extent. Michael White, product marketing manager in the design to silicon division at Mentor Graphics, said that as the International Semiconductor Development Alliance (ISDA) was introducing SOI, there were some unique physical verification activities/checks that needed to be done from a physical verification-DRC perspective that drove the need for parasitic extraction.

“We just want to make sure that the foundries have solutions for Mentor regardless of the process technologies they’re offering to the end fab-lite or fabless customers, so we work very hard to make sure they have decks DRC, LVS and so on. Our tools need to support any functionality required for those alternate flows so that the foundries have complete flexibility to offer whatever process technology they want. We are process-technology agnostic. We just want to make sure that there’s a solution out there if someone thinks it’s appropriate and interesting to use some new process,” he stressed.

White noted that materials and their characteristics have always been a concern. That automatically flows up into the design side from the IDM or foundry as they define the physical verification checks needed to ensure manufacturability. “That’s always been part of the discussion,” he said. “The complexity of the processes due to advanced materials and lithography is going up, and more of that is being captured as physical verification checks and that is driving the complexity of the DRC/LVS checks that folks have to go through now. And because Calibre is the golden signoff tool used by the foundries, we actually get to see that growth in complexity—and it is exploding.”

Specifically, the number of checks was going up 20% to 25% node over node. At 28nm the number is going up faster. Since 28nm was introduced, the industry added about another thousand DRC checks, driven in part by increased complexity in the process. “It’s not just a materials science thing,” said White. “It’s also lithography and other effects that are driving this explosion.

In terms of CMOS vs. SOI, he said the DRC decks seem to be more complex for SOI, and there are more checks in the DRC decks for bulk CMOS.

But moving from CMOS to SOI isn’t so simple, said Matthew Hogan, technical marketing engineer for LVS in Mentor’s design to silicon division.

“If your foundry doesn’t offer SOI then it’s a daunting task of, ‘Do I really want to switch foundries?’ One of the things we are finding from a physical verification perspective, in terms of exploding design rules, is more attention being paid to using some more elaborate checking mechanisms that can actually go in and have a look at the context of the design, Now, instead of having two or three voltage domains, we might have 30, 50 or 100. We are trying to have a look at given the circuit that’s being designed. If I power off, or put a region of the circuit into a standby mode, do I have all of the flip-flops and transistors configured so that it can maintain its state while it’s in this low-power mode? And do I have the correct spacing that I need for the different parts of the design? The verification has definitely become more complicated and the attention to detail has increased greatly for eking out the most power/performance from this technology,” he said.

At this point in time, it’s really about working closely with foundry partners until the time is unavoidable to make the leap to a new semiconductor manufacturing material.