Memory Matters For Mid-Range Mobile Devices

Staying within the power budget requires a number of different power management techniques.


In recent months, we’ve seen signs of saturation in the high-end mobile device market where smartphones and tablets retail for more than $300. The largest growth in the mobile device markets are in Asia, with China in particular showing an annual growth rate of more than 50% in the mid-range ($100-$299) market while low-end products retail for less than $50!

Features like storage capacity, display and camera resolutions, along with the breadth of supported cellular bands are all major factors in product pricing and positioning. High-end features are typically performance driven and thereby come with a power consumption cost. Power-efficiency factors into handset pricing in terms of choice of battery along with the cost of plastics needed to house all the electronics. As high-end features waterfall into mid-range products, the challenge of costs associated with power consumption remain.

While there is no one magical solution to reduce power consumption, a number of different power management techniques are deployed across the system hardware and software hierarchy to stay within a power budget, which is often dictated by acceptable battery life and thermal tolerance of the system.

A significant portion of power consumption occurs in the memory sub-system, which includes DRAM, memory controller and its physical layer (PHY). Certain applications like video recording require a high degree of DRAM access, which increases with resolution and frame rates. This presents some of the worst-case scenarios when it comes to budgeting for power in the system.

Mobile memories go into power down states when not active, and that is fundamentally what makes them suitable for mobile applications. With announcements of 3.2 Gbps LPDDR4 memories, the high end of the mobile device market is now poised to take the next step in terms of performance later this year. Since doubling bandwidth comes with a power penalty, LPDDR4 operates with a lower power supply voltage and employs a LVSTL (Low Voltage Swing Terminated Logic) signaling on the I/Os to save power. Most of the mitigation of the power impact is achieved through the use of LVSTL.

With LPDDR4 targeted at the high-end market, allowing tablets to record and display up to 4K resolution, it will command a price premium for some time while LPDDR3 should waterfall to the mid-range market starting next year. Yet the migration from LPDDR2 to LPDDR3 will come with a power consumption cost. To address these challenges, Rambus has extended LPDDR3 capabilities to a lower power version, called R+LPDDR3.

Rambus’ R+LPDDR3 solution spans the DRAM and the controller PHYs. It leaves the DRAM core unchanged but allows the DRAM die to be configured in either standard LPDDR3 or R+ mode. In R+ mode, this solution employs LVSTL for the data, mask and strobe pins, which is where most of the IO switching activity occurs during normal operation. The power states and the command/addressing scheme of standard LPDDR3 are retained for backward compatibility.

The controller PHY in most commercial application processor SoCs is designed to support multiple flavors of low power DRAMs, with combined LPDDR2/3 support today and upcoming SoC support for LPDDR3/4. Inserting R+ capability into LPDDR3/4 controller PHYs incurs no area penalty, while extending LPDDR2/3 PHYs to R+ involves the addition of the LVSTL drivers and receivers.

As part of the complete memory subsystem solution, Rambus has solidified the PHY designs for both the memory and the controller PHYs, register configuration for R+ operation, the channel characteristics spanning both PoP and chip-to-chip implementation, and the initialization and training sequences for dual mode (standard and R+) operation across the entire sub-system.

Most of the mid-range market uses LPDDR2 memory devices today. The benefit of implementing LVSTL signaling in LPDDR3 offers a 25% reduction in memory sub-system power when compared to a standard LPDDR3, with a solution that is readily usable at production level. With this approach, mid-range mobile device developers can migrate to LPDDR3 levels of performance with minimized impact to their power budget, enabling them to remain cost effective. This is key for the mid-range mobile market.


[…] memory subsystem (for a detailed discussion on this topic see the Rambus SemiEngineering blog: Memory Matters for Mid-Range Mobile Devices). In addition to saving power, staying with DDR3 DRAM saves development costs associated with […]

Sandeep Patil says:

Hi Ajay,
Thanks for the post.

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