Conditions where FPGAs are a solid design choice, what implementation of MIPI in FPGAs looks like, and some use cases for designers.
A new wave of applications for mobile-influenced devices, using technology initially designed for mobile devices, demand high-resolution, high-frame-rate streaming data from vision sensors, especially with the rise of AI inference models performing real-time scene and object classification. These applications include automotive, home automation displays, medical device displays, surveillance and IoT sensors, and more. A natural choice for these designs is vision sensor chips with MIPI® interfaces, which help balance performance with power consumption.
Designers may be able to locate and specify an off-the-shelf vision sensor chip with MIPI that fits their mobile-influenced device requirements. However, a significant decision looms if no off-the-shelf chip meets the needs. Many of these applications require customization to fit in devices with reduced size and power, suggesting the design of a custom system-on-chip. Opportunities in this mobile-influenced space typically present smaller unit volumes, making investments in system-on-chip (SoC) implementations harder to justify with SoC design and fabrication costs rising.
The answer to this conundrum may lie in FPGAs — not huge, power-hungry FPGAs that get most of the attention today, but smaller, more power-efficient FPGAs designed with mobile-influenced devices in mind. These FPGAs offer enough performance for MIPI interfaces running in high-speed or low-power states while leaving room for additional customer-supplied logic in a relatively small package. This article explores conditions where FPGAs are a solid design choice, what implementation of MIPI in FPGAs looks like, and some use cases for designers.
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