Monitoring For In-Die Process Speed Detection

Chip designers working on advanced nodes typically include a fabric of sensors spread across the die for a number of very specific reasons. In this, the second of a three-part blog series, we explore some of the key applications and benefits of these types of sensing solutions. In this installment, the focus is In-Die Process Speed Detection and why understanding in-chip process speed detection alongside thermal & supply conditions is essential if you want to maximize performance and power, improve reliability and ultimately reduce costs your cutting-edge design.

Continued migration to new smaller geometry nodes has brought considerable benefits associated with higher logic density, faster performance and lower power. These benefits come hand in hand with a raft of new challenges which also need addressing. In the previous blog entitled Key Applications for In Chip Monitoring…Thermal Sensing, we touched on the “End of Dennard Scaling” as just one of these challenges.

Why embedded process speed detection?

Process speed has been increasing with each smaller node and with the move from planar to FinFET, but variation between die and also within large die is now a challenge and can make achieving timing closure a real issue. Process monitors within the scribe lane are useful but too far away to give a complete picture of conditions at critical circuits within the die. For these reasons, SoC developers often embed multiple process monitors close to critical circuit blocks across the die to support techniques to improve power and performance.

Speed binning & voltage scaling applications

Example applications for embedded process detectors include speed binning and a range of voltage scaling schemes. Due to process speed variation, silicon from the fab can be either speed binned, whereby the chips are tested and classified into multiple speed bins according to their speed, or the supply voltage can be scaled to achieve a certain performance.

For both speed binning and voltage scaling, a key challenge is at production test; determining the chip speed for speed binning and, in the case of voltage scaling, determining the optimum supply voltage, are both very intensive tasks. One technique to reduce test time is to place process detectors next to critical circuits and select or use external custom ring oscillators to track the speed of critical circuits. Testing the process detectors is much faster than testing the critical circuit blocks. This method does require good characterization of how well the ring oscillators track the critical circuits.

Understanding more about device ageing…

A third interesting application for process detectors on advanced node devices is to monitor and in some cases even adapt for ageing. This can be used for predictive maintenance, for example at the next car service please replace module X because we predict it may fail in the near-term future, or to automatically increase the supply voltage to compensate for circuit ageing. Circuit ageing can be monitored by embedding in-chip process detectors and either measuring and storing information from production test in non-volatile memory as a reference or to include two process detectors. The first process detector is only switched on for the occasional tests and is used as a ‘non-aged’ reference, whilst the second is operated under similar conditions as the critical circuits and so provides a measure of ‘ageing’ when compared with the ‘non-aged’ detector.

For the process detectors it is beneficial to embed these together with a co-located temperature sensor and ideally also with a voltage sense point. This will provide good visibility of conditions at the critical circuits.

With Moortec’s modular in chip monitoring IP, further temperature sensors can be embedded elsewhere to monitor hotspots on their own and also voltage sense points can be placed individually. You can read more about the importance of embedded voltage monitoring in the last blog of this series which will be available soon.

Advanced node challenges & in-die process speed detection

SoC developers are facing a range of new challenges when designing on advanced process nodes, especially FinFET, and process speed variation not just from die to die but even within large die should be considered when optimizing power and performance. To help address these challenges, a common strategy is to embed a fabric of in-chip monitors across the die. These give visibility into on chip conditions, which is especially valuable for critical circuit blocks. On chip process detectors located near critical circuits can support dramatically speeding up testing for speed binning or voltage scaling as discussed above.

In-chip monitoring really is now fundamental for all developers who wish to obtain the maximum from their SoC whether it is performance, power consumption, or reliability or a combination of all of these.

So, if this blog has got you thinking more about the effects of process variation in your existing or next design, why not contact Moortec today to find out more.