Moore’s Law Will Never End

Moore’s Law has been many things to many people. It has been a statement of physical limits and an economic formula. It has been the cause of overheating and complex power solutions, and it has been a competitive weapon among companies looking to boost performance and cut costs.

It also has been revised on more than one occasion as the time frame in which the number of transistors doubles has floated between 18 and 24 months. And it has been predicted to die on multiple occasions, starting back at 1 micron (aka 1,000nm) when lithography was believed to be at its physical limit.

Moore’s Law has defied all predictions and all odds. Some companies have jumped off the bandwagon and moved in different directions, while the largest continue to adhere to its advancement with almost religious fervor. But the real future of Moore’s Law be less of a mark of size of the company making the investment in a new chip than a piece of an overall system that limits the use of advanced process nodes for extremely regular structures in places where space matters but little else.

As we move into 3D stacking over the next few years and tighter integration between software and system design, the real future of Moore’s Law may be less impact on the overall system and less importance for what makes one chip different from another. Rather than come to an abrupt end, Moore’s Law may be the part of the chip that is most commoditized rather than the part that wields the competitive edge.

This is a rather shocking end game for a formula that has dictated how chips were developed throughout most of the history of ICs. But it also means that companies will need to start looking beyond Moore’s Law and replacing it with new formulas, approaches and structures—ones that may have far less impact over the long haul but which will be just as important for the generation of semiconductors that benefit from them. The same variables of area, power and performance still matter, but they will no longer be defined by the line width between all the components on a chip.

–Ed Sperling