More Than Meets The Eye: Trends In Lithography

Lithography, once the exclusive domain of artists and printmakers, also lies at the heart of integrated circuit (IC) production. The process of shining light on a substrate through a photomask to control exposure has been around since the 1960s and has been the key part of improving IC fabrication process resolution. At the time, the light sources used were in the human-visible spectrum, which sufficed down to a feature size of about a micron. As the title of this post suggests, this is no longer the case. Today’s deep submicron ICs require extreme ultraviolet (EUV) light lithography, and a great deal of innovation has gone into making this work for ever smaller process nodes.

One significant historical trend has been the evolution of light sources. Mercury lamps were replaced by excimer lasers in the 1990s. This took the industry from krypton fluoride (KrF) lasers through ArF (argon fluoride) and into an ArF immersion process. In recent years, as feature sizes have pushed below 30nm, laser produced plasma has become the norm. Plasmas created by high power pulsed lasers are a good source for very short EUV wavelength radiation. This enables the EUV lithography era of today, which is likely to continue for the foreseeable future.

Initially, EUV became the leading lithography solution with low NA (numerical aperture) EUV, which enabled patterning down to about 15nm. Now high NA lithography can achieve nearly three times greater feature density, critical for IC device nodes of 2nm and smaller. Although NA EUV is enabling tighter resolution, the anamorphic imaging method used is now requiring the exposure of two masks to achieve the standard 26x33mm field size on wafer. The process of stitching together multiple exposures for high NA EUV is challenging due to double exposure effects at the stitch boundaries. The emergence of stitch-aware design rules and stitch-friendly physical design is another important trend in the IC industry to help mitigate lithography challenges in these stitching regions. Effectively handling the overlapping exposures in the stitching region and the difficulties associated with them are expected to become even more common as high NA tools replace low NA solutions on more device layers in the patterning process.

The trend toward high NA EUV, which is beneficial in driving to smaller feature sizes, introduces additional challenges. New extensions are needed to the optical proximity correction (OPC) and resolution enhancement technology (RET) mask synthesis steps to correct for imaging errors and to more faithfully reproduce the designed pattern on wafer. Edge placement error (EPE), the difference between the intended and actual circuit features, is another challenge that gets even harder with high NA EUV. Optimized sub-resolution grating (SRG) feature placement is also becoming important to reduce double exposure background dose effects. Inverse lithography technology (ILT) holds much promise with flexible cost functions to deliver optimal mask corrections in these overlapping regions.

The final trend to consider is the rise of artificial intelligence (AI) in the lithography process and the electronic design automation (EDA) tools that support it. Machine learning (ML) and deep learning (DL) techniques can benefit EUV lithography. As in other areas of EDA, the ability to apply the knowledge base from prior IC designs and previous iterations of the current design leads to faster convergence and better results to address many of challenges noted above. Although generative AI is not yet a mainstream solution in this domain, studies have shown that it will soon enable more efficient and cost-effective, production-level flows for generating layout and mask datasets, including OPC and ILT.

In the era of high-NA EUV, IC lithography is very complex but quite exciting. If you’d like to learn much more, there are two excellent opportunities coming very soon. On February 24, the Synopsys Technical Forum 2025 (register here) will be held in San Jose, CA. Sessions will cover the latest industry trends, including many of the topics touched on here, along with solutions for mask synthesis, mask data prep, and lithography simulation. In addition, IC industry experts, including speakers from IBM, Intel, Micron, Texas Instruments, and Fujifilm will share their insights and opinions on EUV, AI, and other important lithography trends.

The forum is co-located with the SPIE Advanced Lithography + Patterning conference on February 23-27. SPIE is the international society for optics and photonics, an excellent source for expertise in lithography and related fields. Synopsys is very active at this event and will present a keynote on the impact of AI on IC development as well as eleven technical papers. These papers include three directly related to high-NA EUV, including the use of generative AI, stitching-aware OPC/RET, and mitigation of stitching-induced performance and yield losses. Don’t miss these two events to learn more about key trends and solutions for IC lithography in the EUV era.