New Low-Power Memory Technology Under Development

High density, vertical stacking could open the door to terabytes of cheap, monolithic memory.

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By Pallab Chatterjee

Unity Semiconductor, which was formed in 2002 and has been in stealth mode until May of 2009, is progressing on the development of a very dense and low power non-volatile solid state memory technology.

Unlike traditional semiconductor memory, which uses an active device and electron transport as the primary storage element, the Unity Semiconductor CMOx technology uses a new ionic oxide element for the storage node. The technology appears to use a similar hysteresis waveform performance as the recently identified HP Memristor, but it uses a different energy profile in write and store and a 1 vs. a 0 along with a non-linear I-V curve. Although the wave shape has been observed in semiconductors since the 1950’s and theorized since the 1970’s, the device has not had intentional implementations and circuits until the sub-180nm era of processing.

Based on discussions with Christophe Chevallier, Unity’s vice president of design engineering, the solution at Unity is based on a traditional CMOS logic process to create the base logic and addressing/ECC control for the memory (currently in 130nm and moving to 90nm for production), and then a special memory material back-end of line (BEOL) process (currently on 130nm and moving to 45nm/35nm for production).

The base wafers are being built by TSMC and with a major Japanese ASIC supplier. The BEOL flow is local to the United States. The process and device characterization was developed by Unity. The use of multiple process nodes allows for optimization of performance, cost and power (operating and leakage) for the design while minimizing the facility investment.

The core memory is a cross-point array architecture and is based on optimal use of the transistor-less vertical memory element. This is shown in the diagram below, which details the sections of the memory element. These memory cells, due to their programming method and device operation, are no longer limited to being planar pitched devices. They can be stacked vertically.

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At this time Unity’s characterization chip (a 64MB design) is using a single-level cell (see device cross section below, including the visible layer stratification for the memory elements), but the company has conducted other test designs showing the technology is stackable in the BEOL processing up to 8 layers of memory element. The initial product will use a four-layer stack. The core cell figures of merit and anticipated larger production die are based on this four-layer stack.

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The photo below shows the configuration for the four-layer stack and is the method that is targeted for Unity’s xTB-sized chips.

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Since the BEOL processing does not require any high temperature flows (anything over 400C), the native logic device operation is unaffected, which allows for optimization of the design to low leakage and very low standby currents. The current designs and their associated internal IP have all been created using standard Cadence analog and custom design tools and industry standard simulators.

The use of the stacked memory and vertical conduction/programming path for the very small data store element minimizes the interconnect RC and associated parasitic and thus the size of the drivers needed. The memory element has a fairly large (proportional to other memory technologies in the same size form factor) detectable signal, which lets the sense circuitry operate at lower operating power compared to other similarly sized cores.

The optimization of density and power has targeted the CMOx memory products for SSD class storage. While it will be compatible with traditional NAND Flash applications, its higher density and power will direct the product into the high-capacity applications. Both netbook/notebook and enterprise class SSD devices are being targeted.

The products will use traditional DDR memory interfaces. The new technology, by virtue of supporting the cross-point memory architecture, allows for different memory addressing options and error corrections method including byte-wide and page-at-a-time write capabilities, and correction levels from a single cell being skipped to dropping an entire plane of the memory elements.

Unity said its technology is protected by many patents (more than 50, so far, with more in process) and seems to be working with the split manufacturing facility method for the current time. If successful, along with HP’s entrance into the memristor memory market (similar density numbers), terabyte-level monolithic memory should be cheap and available to all who need it.