No More Netlist Hacking

Electrical rule checking becomes a requirement to protect against electrostatic discharge and cross-domain problems.


By Ann Steffora Mutschler
Prior to availability of advanced physical verification tools, it was not uncommon for engineering teams to hack netlists. It sounds very clandestine, but was done out of the need to get detailed information on particular areas of the chip suspected to be a problem.

Performing electrical rules checks (ERC) to improve the correctness and reliability of IC designs before committing to manufacturing is essential since catastrophic electrical failures of the IC can occur during factory test, transport, and field operation. Specifically, electrostatic discharge (ESD) protection circuit checking, cross-domain and multi-cross-domain protection checking, level shifter checking, and optimal ESD I/O placement checking are done to identify areas of vulnerability.

The biggest challenges in ERC fall into two camps: verification across multiple power domains, and verification for possible ESD failures, according to Carey Robertson, product marketing director for LVS and extraction at Mentor Graphics.

Obviously, mixed signal design is not something new, but is causing new challenges. “We’ve been designing in various power domains for some time but we have one customer that has 30 to 40 different areas on their chip in different power domains. It’s not 30 to 40 unique power domains – they are spreading out blocks across a variety of analog, digital and memory components that are operating in different voltage ranges.”

The challenge with multiple power domains is that there could be a transistor operating at 3.3 volts connected to a data path or a signal that goes to a transistor that should operate in the 1.5-volt range. In this case, if the appropriate circuitry—level shifting—is not implemented to bring that voltage down, there will be an immediate failure or a degradation of that transistor over time.

Level shifters are used when there are multiple voltage islands. Whenever there are different parts of the chip operating at different voltages, they need to be protected properly so that, for example, a high-voltage region does not try to send a high voltage into a lower voltage region. That would cause the lower-voltage circuitry to malfunction. Essentially, level shifters shift voltages at the power domain boundaries.

Complicating all of this, design teams are combining more and more pieces of IP that are not necessarily designed by them, Robertson observed, “so they essentially have these hard macros they can’t change. In terms of what challenges the process node brings, it does bring very thin oxide transistors.”

In fact, there is some speculation in the industry that the recent Intel error is due to a thin-oxide transistor failure. The thinner these oxides get, the less robust they are to these types of issues.

ERC has been used for 20 years or more. Typically it is done using traditional physical verification tools DRC/LVS, which look at a single node/single transistor and the voltages and the wells that it resides in to find out some fairly basic errors. SPICE circuit simulation also can be used, but is very expensive and can’t be done at a full-chip level.

Thin oxide has also driven the need for earlier ERC. “You’ve got a catastrophic failure very, very soon, as opposed to if you did this at 65nm it may be a longer-term degradation and maybe you don’t see it as soon. Definitely you’ve got to check it sooner,” Robertson said.

Another reason for earlier ERC is that what could be done at 65nm with some hand inspection or manual inspection does not cut it any longer. “If you’ve got 30 to 40 blocks that are talking to each other and you are not exactly intimate with how those blocks were designed, these manual checks are error prone, and the need for more automatic methods is higher,” he added.

ESD challenges growing
When it comes to SoC ESD requirements, the challenges are mounting, as smaller manufacturing process technologies require thinner gate-oxides for MOS devices.

“Physically a thinner oxide is more susceptible to breakdown.,” said Navraj Nandra, director of analog/mixed signal marketing at Synopsys. “New devices such as active snap-backs that use thyristor properties, transistor-based clamps, and level shifters with grounded gates are being implemented. Support is required for both primary and secondary ESD protection. This means there must be capability to check across ESD domains. The ESD clamps that are used for CDM—simplistically back-to-back diodes—need to be carefully scaled for the appropriate technology node and level of protection. It is possible to increase the protection at the cost of area. Another very important requirement is to follow careful layout techniques that maintain the integrity of the foundry design rules but still provide ESD robustness. This is certainly becoming important at 40nm and 28nm. The trend is to reduce amount of ESD protection on the SoC and to add dedicated ESD devices externally.”

Apache Design Solutions has been focused on ESD for some time.
“ESD traditionally is always a problem. We call it the ‘human body model.’ When you zap it the device can be destroyed because there is too much charge,” said Dian Yang, general manager and senior VP of product management at Apache.

A new test mode called CDM (charged device model) is now being used to define the ESD a device can withstand when the device itself has an electrostatic charge and discharges due to metal contact. That’s the most common type of ESD in electronic devices and causes most of the ESD damage in their manufacturing.

“CDM happens during the manufacturing assembly line,” Yang explained. “So when you have a chip and you move the die from one place to another for assembly purposes, testing or packaging, it goes through an assembly line. During this process, it accumulates electrons. When you move it to a certain point, if something—a robot, for example—touches it then it can have a huge discharge. That is a big problem for yield. This happens so often that the yield really becomes low. In fact, some of our key customers got big hits because of this. It directly affects profit and their bottom line.”

To protect from CDM failures, the assembly line has to have appropriate protections to make sure it doesn’t accumulate a lot of static charge. Another way to protect from CDM is that when the chip is built, it contains a lot of ESD devices, he said.

Even so, CDM is becoming a very big problem for yield loss.

However, just adding ESD devices is not simple because ESD devices are not manufactured in a normal CMOS process. As such, they do not follow traditional scaling rules. “If you reserve 5% of your die for ESD devices, when you do a process shrink that 5% becomes 40%, so your whole die is occupied by ESD devices. That’s useless in normal cases, and Moore’s Law doesn’t work any more. That is the second reason why ESD is becoming more and more important, because people want to use less and less ESD devices on the chip,” Yang noted.

A third reason for the increasing need for ESD protection is low-power design with the widespread use of voltage islands. To adequately protect from ESD, every power domain must have a certain number of ESD devices. With designers needing to use fewer of them, they need to know how to minimize their risk and still achieve a low-power design. “On the one side, low-power design requires more voltage domains, but on the other side more voltage domains require more ESD devices. You can’t put in all of the ESD diodes, so we check that based on certain criteria (resistance checking/current density checking) to see if there are enough ESD devices or not,” he added.

Before these tools were available, a lot of design teams were hacking netlists. “They would take a power net, run a script and try to get the parasitics for just that area of interest. That required a combination of techniques of scripting on netlists, trying to get a DRC/LVS tool to give them some data that would be a proxy for this type of verification, and also a lot of manual design reviews – having the senior designer look at the junior designer’s schematic,” Mentor’s Robertson said.

That’s beginning to change as tools become available. It’s interesting to note that each vendor takes a different approach with the tools. Some have standalone tools, while other have incorporated ERC into other physical verification tools.

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