NoC Technology: Saving the Planet, One Chip at a Time

In Silicon Valley, the cliché is that we are using technology to change the world in some meaningful way. However, I made some calculations recently and I found network-on-chip technology is actually contributing to efforts to reduce carbon emissions.

SoC designers have become the ultimate energy misers as they strive to make tradeoffs between extending battery life and providing game-changing performance for systems. Nowhere are these efforts more prominent than in mobile application processors where a mere milliwatt of power consumption can mean the difference between a design win in market-leading consumer device or the loss of an opportunity to participate in a high-volume, rapid growth market.

Designers have reduced SoC power consumption by switching from a hybrid-bus interconnect architecture to an advanced network-on-chip interconnect fabric. One project team told me that implementing NoC in a mobile applications processor had reduced active power consumption by 0.7 milliwatts over a 1-million gate block.

According to the U.S. Environmental Protection Agency, saving even 0.7 milliwatts of power consumption can eliminate 4.2 kilotons of CO2 emissions per year when it is spread over 1 billion mobile phones. As you can see, the global switchover to advanced NoC technology is helping to save the planet, one chip at a time.

Above left, a chip with a traditional hybrid bus architecture is shown and on the right, an SoC interconnect using NoC technology, reduces wire congestion and saves power consumption.

However, SoC power management is also gaining prominence in a number of new and traditional markets ranging from data center CPUs, and automotive infotainment to IoT devices and wearable systems. Therefore, any measure that can make a substantial difference in decreasing power consumption is a make-or-break capability.

While CPUs and GPUs dominate the power management attention of most SoC projects, other functional blocks are gaining in awareness for the power-conscious.

What if your design team was presented with following opportunities:

• Decrease active power consumption 0.7 milliwatts over a 1-million gate block;
• Reduce die size by 3-square millimeters;
• Drop idle leakage power by 7x;
• Cut the number of wires by 50%;
• Shrink gate count by 30% to 50%;
• Eliminate routing congestion.

Today, interconnect technology remains an afterthought in many fabless SoC design teams. But the results provided above are commonplace for those that have switched to advanced NoC interconnect fabrics. And many of those teams have achieved volume leadership in key mobility segments.

One of the most prominent advantages of NoC technology is the ability to manage power consumption across all the functional blocks on the SoC and all the connections between them, and not just the CPU and GPU. Since the interconnect touches all blocks of a design, it provides the ideal opportunity to enhance best practices in the following areas:

• Data path optimization and performance modeling;
• Voltage/power/clock domain partitioning;
• Power disconnect protocol;
• Asynchronous clock domain crossing;
• Clock gating – fine-grained and unit-level;
• Partial retention;
• Performance probe used as feedback for DVFS;
• Automation;
• SoC analytics.

A closer examination of some of these items reveals advantages that NoC technology provides over older hybrid bus and cross-bar interconnect technology.

Data path optimization and performance modeling
Because of the NoC benefits of data packetization and flexible serialization, the data path width of each link in a NoC can be independently configured. As a result, all buses and logic within a NoC can be as small as possible within the constraint of their bandwidth and latency requirements.

A scalable network avoids the need for building separate switches and bridges to scale interconnectivity. A configurable NoC allows the use of different amounts and types of buffering for each location. These flexibilities minimize area and therefore reduce leakage power consumption.

Overdesign wastes power. Accurate and insightful tools to analyze performance and pinpoint limitations allow thorough exploration of possible design trade-offs and a near-optimal result.

Voltage/power/clock domain partitioning
Because NoC technology is what connects IPs, it is an excellent mechanism to separate IPs into different power, clock, and voltage domains. NoC technology enables all blocks to be power-controlled individually. This adds finer granularity with software-controlled block partitioning.

Finer granularity partitioning enables a greater portion of the chip to be turned off in different use cases. For example, when rendering scenes with few polygons or at low resolution, only a portion of a GPU array needs be powered up at full voltage and clock frequency.

Power savings within the NoC fabric
SoC designers can implement power-down of domains using standard protocol for communication between a SoC-level power management unit (PMU) and local power disconnect units within the NoC. The protocol safely handles fencing by responding safely to incoming request to powered-down targets. It also handles draining, or the completion of pending transactions to and from IPs in the domain to be powered down and eliminating the potential for system deadlocks. A NoC configuration tool can simplify and automate the generation of power and clock disconnects within the internal transport topology.

It’s important to note that if a design team hopes to have success in a market where reducing power consumption is critical, it has to at least match or surpass the energy-saving efforts of the volume leaders. NoC IP plays an integral role in the mobile application processors and LTE digital baseband modems of many of today’s leading smartphones and tablets, where the tradeoff between extending battery life and improving performance figures prominently among all design concerns.