New ways to cut test costs and speed up time to market.
With the growth in design size and complexity, DFT engineers began adopting new methods to reduce DFT implementation time, reduce test costs, and reduce risks to design schedules by removing DFT from the critical path to tapeout. The primary method to accomplish large improvements to DFT efficiency is through a divide-and-conquer approach supported by Tessent’s RTL-based, hierarchical DFT insertion, validation, and pattern generation. Creating all the DFT at the core level then retargeting the core-level work to the chip-level has been widely proven to save time, save money, and reduce risk.
Tessent Connect addresses the challenges of adopting and implementing hierarchical DFT flows.
To read more, click here.
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