A technical paper titled “Optimizing Offload Performance in Heterogeneous MPSoCs” was published by researchers at ETH Zurich.
“Heterogeneous multi-core architectures combine a few “host” cores, optimized for single-thread performance, with many small energy-efficient “accelerator” cores for data-parallel processing, on a single chip. Offloading a computation to the many-core acceleration fabric introduces a communication and synchronization cost which reduces the speedup attainable on the accelerator, particularly for small and fine-grained parallel tasks. We demonstrate that by co-designing the hardware and offload routines, we can increase the speedup of an offloaded DAXPY kernel by as much as 47.9%. Furthermore, we show that it is possible to accurately model the runtime of an offloaded application, accounting for the offload overheads, with as low as 1% MAPE error, enabling optimal offload decisions under offload execution time constraints.”
Find the technical paper here. Published April 2024 (preprint).
Colagrande, Luca, and Luca Benini. “Optimizing Offload Performance in Heterogeneous MPSoCs.” arXiv preprint arXiv:2404.01908 (2024).
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