Packaging’s Power Play

Why the packaging team has suddenly becoming popular among chip architects and designers.


By Ann Steffora Mutschler

In the not-too-distant past packaging was not an issue IC designers had to think much about. But now, due to smaller geometries and rising complexity, managing power in the entire system has become a major concern for system architects.

IC and package designers now must work closely throughout the design process to make sure no surprises come up down the road. And given that the cost of the package can be 30% to 50% of the IC, packaging design has been thrust into the minds of design engineers at all levels.

Ceramic and organic materials are the two main classes of materials used today in semiconductor packaging. Ceramic is more expensive but allows more layers in the package, which tends to give better power integrity, explained Brad Griffin, product management director at Cadence whose focus is high-speed analysis for PCBs and packaging.

Overall, there are three areas of power that must be addressed in the package: power needs to be supplied sufficiently to the chip through the package, it needs to be done efficiently (cheaply), and the power needs to be stable. There are a lot of tradeoffs that come into play over this.

“From a materials perspective, a ceramic package can provide more layers than an organic package typically would,” said Griffin. “It can allow you to provide sufficient and stable power, but because it is more expensive it’s not typically as efficient. Since cost always becomes the biggest issue—engineers are always looking for ways to do sufficient and stable power in organic package because that’s going to be less expensive.

Also important to note are the two typical ways that a die gets attached to a package, through wire bond and flip chip. “To be able to deliver sufficient and stable power, it is a lot easier through the flip chip because that’s the approach where you’re not going to have to get a large amount of current through the wire, but wire bond is cheaper so people are always trying to do that efficiently while maintaining sufficient and stable power,” Griffin said.

These issues have driven the need to include packaging in power analysis activities. And while this is not widespread today, it is on a quick ramp at advanced nodes.

Dian Yang, general manager and senior VP of product management at Apache Design Solutions pointed out that the package in theory should have been included a long time ago, but in practice it’s not. “For low-power design, the one big thing is to lower the voltage. We start from 2.5v, and then go down to 2.0, 1.8, 1.5, and 1.2 now down to 1 volt. And when you lower the voltage, you have less margin to play with because the threshold voltage for transistors is pretty fixed. That means from your operating mode to your threshold voltage, you have about 400 or 500 millivolts. But if you look at the power source from your battery, it goes through the board, it goes through the package then gets to the transistor – along the way it will drop a lot of volts. When this aggregated dropping (aka voltage droop) exceeds the margin, that’s the time you really need to analyze. In theory it is below 1.2 volts.”

Another factor here is how much current the IC consumes. If the whole IC consumes more current and needs more power, the voltage droop will become bigger and more significant. “Because people are putting more and more transistors on a die you have more transistors simultaneously switching, and that drops a lot of power at the same time,” he explained.

From Mentor Graphics’ point of view, John Isaac, marketing programs manager for board system design in the systems design division said, “We look at the power from the point of view of not trying to limit the power – that’s the job of the IC guys – but what do you do with it when you have these high power ICs and packages generating a whole bunch of heat. How do you get it out of there—but from a packaging design point of view—from the IC out to the heat sinks or onto the PCB, and then from the heat sinks and PCBs, out to the system?”

Mentor’s approach is to characterize and analyze the heat paths, power dissipation and heat dissipation capabilities of a package. “From that point of view you are able to, with the data that it captures, create a thermal model for that package. You iterate on different package designs, come up with the best one, test it from a hardware point of view, and create a thermal model for that package. From that, you can then do thermal analysis at the package level, at the PCB level and finally, the whole system level using real computational fluid dynamics and some very sophisticated algorithms to get rid of that heat.”

Given this data, how do engineers choose the right package? Obviously, they look to the package with the lowest cost and the fewest number of layers, but both of these things can increase the parasitics of the package—making the power integrity worse, Yang pointed out.

Understanding the separation between IC designers and package designers is part of the answer here. “The fundamental problem with IC designers is that traditionally, they have been isolated from the package. But to select the right package for the proper die you really need these two groups to start talking very early, not after the design is done. That’s too late. This means even at the architectural level of design you already need to decide what package to use (how big the package is, how many power pins/bumps/pads, how many layers of substrate, type of package, etc.). All of these decisions should be made at that time, and that’s a challenge,” he said.

While this is not a widespread practice today, Yang said Apache has observed a few large companies move their package group into their IC design group. This is turn has propelled the packaging houses to work closely with IC designers, which is a relatively new practice. These changes are also bringing vendors into new alliances, such as those between foundries, packaging companies and EDA vendors.

Jamil Kawa, group director for R&D in Synopsys’ implementation group agreed. “The design methodology for the system instead of bottom up, it’s becoming top down. If you are the architect of a cell phone, for example, you’ve defined the chips or blocks that are going to go on the tiny PCB board in the phone. Then you franchise this design. You assign the chip and for each chip the designer will pick the optimal technology. Then the board designer has to have those chips talk to each other. The methodology is bottoms up. Everyone does their corner. That is out of the door for two reasons: power and noise. The new approach, which includes some very intensive optimization and simulation at the system level, starts with the overall system, building the board to minimize the connections to eliminate any potential reflections, surges, etc. noise issues from the board. From there, you define the pin-out of each block.”

Not to be forgotten is the impact of 3D ICs on packaging and power. Before 3D ICs began appearing on the horizon, the only way to get signals and power to die that are stacked was through wire bonds. On a single die, flip chip vs. wire bond, there is going to be much better power control with the flip chip so effectively with TSVs and stacking die you’re basically getting that same level of stability up the chips in a stack almost as if they were direct attached to the substrate, like a flip chip. Again, it’s overcoming that lack of sufficiency and lack of stability that you have when you go through a wire, through a direct connect, through a TSV, Cadence’s Griffin explained.

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