Performance Analysis On Dark Silicon

How to do ‘light’ vs. ‘dark’ silicon performance analysis.


It’s one thing to do performance analysis on the ‘light’ parts of an SoC design, but what about when most of the silicon is ‘dark?’

Jon McDonald, technical marketing engineer at Mentor Graphics stressed that modeling the effects of turning on and off sections of the silicon is an important part of creating an accurate representation of the system. “Our models support state-based power and timing effects, the timing to perform an operation may be much longer if it’s starting from a low power or power off state.  This is actually a critical aspect of  performance analysis and can be difficult to perform in RTL.  Generally  analyzing these effects require representative workload models that may involve full user applications and OSes running on the platform to define the use case.”

Drew Wingard, CTO of Sonics sees two models when it comes to performance analysis of dark silicon. “The first model is the one that is practiced most directly – if the power control is done on software then you know that on this use case that silicon is dark. They don’t analyze it. Basically you think of the power control as being a side effect of the use case that you were running so you can clearly abstract away the parts that are off. But of course that leaves power on the table.”

What Sonics sees happening in the most advanced systems that is power control is far more dynamic than that so the engineering team has to think about the implications of what happens in an ideal world where everything was on all the time, he said. “For example, I know that there is no latency penalty associated with communicating with this element. But in the actual system it may well be powered down at the moment but I want to speak with it so I am going to have to wait and how do I factor that into my performance analysis?”

This means that the power architecture plays a role in the performance architecture, Wingard offered. “One of the reasons we think there’s a good synergy between the on-chip network and the power management control system is the fact that when we ask people, ‘What are the use cases you use for analyzing the performance of your design, and what are the use cases you use for analyzing the power of your design?’ they are pretty well aligned so by thinking about a common environment in which you capture that information to capture some of those use cases so that you can use it essentially for a codesign of both the memory system and fabric architecture as well as the power architecture seems to make a lot of sense.”

Frank Schirrmeister, senior group director, product management in the System & Verification Group at Cadence agreed. He also pointed out that engineering teams actually use the performance analysis to decide when it can go dark.

Performance analysis shows the difference states and scenarios the system is in and that actually helps engineering teams make the decision when something can be switched off or when something needs to be switched off for thermal reasons, Schirrmeister explained. “I need to be able to take the performance data into consideration to understand when to switch things on and off. Performance analysis is a big issue because it is giving you a lot of the differentiation in the design.”

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