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The High But Often Unnecessary Cost Of Coherence


Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized accelerators and other processing elements. While cache coherency won't disappear anytime soon, it is increasingly being viewed as a luxury necessary to preserve a long-standing programming paradig... » read more

Arm Neoverse N1 Core: Performance Analysis Methodology


The Arm Neoverse ecosystem is growing substantially with many Arm hardware and software partners developing applications and porting their workloads onto Arm-based cloud instances. With Neoverse N1 based systems becoming widely available, many real-world workloads are showing very competitive performance and significant cost savings when compared to legacy systems. Some recent examples include:... » read more

What’s Next For Emulation


Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

Performance Analysis Of Electric Motors For EV Powertrains


Developing a battery EV powertrain is a complex systems problem. This technical paper examines the design and development of electric motors in an EV powertrain, showing how the different design choices — such as motor topology, winding type and cooling system — can be compared and evaluated considering their overall system impact. ANSYS Motor-CAD simulations can help engineers determine wh... » read more

Verdi Transaction Debug Solution: Unified Performance Analysis And Debug For Interconnect


In modern systems on chip (SoCs), where Arm AMBA protocols are intensively used as standard intellectual property (IP) interfaces, the interconnect is usually required to bridge and facilitate the communication between many different IP interfaces. The interconnect presents one of the biggest challenges of SoC verification, considering the different kinds of protocol interfaces, conversion of d... » read more

Analyzing Testbench Design Performance Using Verdi Performance Analyzer


Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. This paper describes the challenge to measure design performance and explains how Verdi Performance Analyzer enables run ti... » read more

System Performance Analysis At ARM


Performance analysis is a vital task in modern SoC design. An under-designed SoC may run too slowly to keep up with the demands of the system. An over-designed SoC will consume too much power and require more expensive IP blocks. At ARM we want to help our partners build SoCs that deliver the best performance within their power and area budgets. The simple truth is that this is more difficul... » read more

Deciphering Performance Analysis


Simulation traditionally has been the go-to technology for improving system performance, but practices are evolving and maturing because engineering teams need to be able to simulate in multiple domains and at at multiple levels of abstraction. In addition, they need to tune the level of [getkc id="11" kc_name="simulation"] they are using to what types of models they have available, and what ki... » read more

Performance Analysis On Dark Silicon


It’s one thing to do performance analysis on the ‘light’ parts of an SoC design, but what about when most of the silicon is ‘dark?’ Jon McDonald, technical marketing engineer at Mentor Graphics stressed that modeling the effects of turning on and off sections of the silicon is an important part of creating an accurate representation of the system. “Our models support state-based... » read more

Experts At The Table: Performance Analysis


By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more