Performance Plus Lower Power

A new race is beginning in the SoC world. While performance has been supplanted by battery life as the top goal for the next process node, that prioritization isn’t going to last. The ultimate challenge will be to achieve both—higher performance with substantially lower power.

This is the subject of research inside of dozens of companies and universities, and there are several different approaches being taken. The reason is that while existing performance levels will suffice for awhile, particularly in mobile devices, the competitive edge in the future will be provided by faster searches, connections, better quality for streaming video and—yes—fewer dropped calls. But it will all have to happen using a battery that can last a day or more between charges, even while operating at full tilt. And it also will have to happen using existing battery technology, because improvements in that area are extremely slow.

There are four main approaches to this problem. One is to develop chips that can power down and up much more quickly, with much bigger swings between the two. Work in this area ranges from different memory technology to different gate structures and new materials.

A second well-publicized approach is the 2.5D and 3D stacking of die. The advantage with stacked die is that it takes less power to drive signals because the distances are shorter and the pipes through which signals travel—either TSVs or interposers—are much wider. The challenge in this area will be getting packaging costs under control and providing a more consistent TSV manufacturing process.

A third approach will be to supplement this with some sort of energy scavenging technology that can either power devices or simply amplify the signal so that mobile communications require far less power. Work is under way to improve base station technology, as well, so that signals can be shared across multiple towers.

And finally, there is work under way to significantly lower the operating voltage inside of SoCs, which is probably the longest-range approach because it will require changes at the gate level and in memory to be able to retain data and functionality.

It’s likely that no single approach will suffice. A combination of two or more of these approaches may be be necessary, along with tweaks at every level to reduce leakage, improve throughput, eliminate bottlenecks and minimize physical effects. Taken separately each of these approaches represents a big step forward, but taken together they can change the power/performance equation forever.