Timing Is Of The Essence


Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

Tech Talk: Extending DRAM


Bruce Bateman, senior principal engineer at Kilopass, talks about how to extend the life of DRAM and how to work with smaller, denser memory.   Related Stories Executive Insight: Charlie Cheng Kilopass’ CEO talks about how to cut the capacitor in DRAM and why that’s important in the data center. » read more

Performance Plus Lower Power


A new race is beginning in the SoC world. While performance has been supplanted by battery life as the top goal for the next process node, that prioritization isn’t going to last. The ultimate challenge will be to achieve both—higher performance with substantially lower power. This is the subject of research inside of dozens of companies and universities, and there are several different... » read more