Planning For Physical Effects

The push into 3D structures and 3D stacking will change SoC design, but not always in expected ways.


The importance of Intel’s announcement that it has perfected 3D transistors and will roll them out this year should not be understated. This is a major breakthrough technologically, with major implications for power, performance and even competitiveness. FinFETs have been the subject of some intensive research for more than a decade, with the University of California at Berkeley leading the charge.

This is the first of several major shifts that will begin over the next few process nodes. One will involve lithography, where double patterning and computational scaling will become more prevalent starting at 22nm. The second involves the proliferation of lots more 3D structures on wafers, including everything from multi-gate transistors such as Intel’s tri-gate FinFETs to MEMS devices and 3D memory. A third involves stacking of die, which is expected to bridge multiple process nodes together initially, with more complete modeling and the proliferation of through-silicon vias over time.

What’s becoming clear is that we’ve just scratched the surface when it comes to power and performance. Wide I/O, right-sized processor cores, more efficient software, co-development of hardware and software and better connectivity externally and internally will provide significant boosts in performance while also cutting power consumption. There are huge gains to be made over the next couple nodes in both areas.

What few people are talking about, however, are the physical effects that need to be considered in developing this new breed of chips. Time-to-market pressures will force much more re-use, more concurrent design and more experimentation with new ways of making that happen faster. But in the rush to get chips out the door, there will be all sorts of new challenges to deal with. How do EMI and ESD change in a chip that is densely packed with FinFETs, for example? How do vertical stacks and vertical structures affect noise-sensitive analog IP? And what happens when you start mixing firmware, software and hardware with third-party IP? How does all of this affect timing closure? And what sort of impact will there be from turning on and off segments of a chip that may include lots of 3D structures in a 3D stack?

We have come a long way in verifying the functional aspects of SoCs. The next big challenge will be understanding the physical effects and how to model them effectively. The introduction of FinFETs is a major step forward, but we still have a long way to go to really understand how all the pieces fit together.

–Ed Sperling

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