A look at the power and signal integrity verification flow.
Power grid verification is a challenge, and there are no industry standards for design teams to follow that will verify the power grid for power and signal integrity issues. In other areas there is typically a verification plan with checks to perform, and when successfully completed, the design is then considered verified to proceed to tape-out.
Having high coverage in the power grid’s power and signal integrity means that post tape-out designs will not experience a logic failure because a critical timing path was violated. It will also avoid an analog design becoming non-functional due to a noise level that was beyond its specifications, or a jitter target violation on the DDR chip clock pin.
This paper will present a verification flow for high power grid verification coverage, with little effort, while identifying weak points early in the design cycle.
To read more, click here.
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